From a1e7ab6f82786032fe7d02ec70abc65b5ca3a9ad Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 7 May 2021 10:46:29 +0800 Subject: soc/mediatek/mt8195: change vpp_sel default mux for 4k support vpp_sel and ethdr_sel are vdosys clock source select mux. Steps to change to support 4K source. 1. Change vpp_sel source to mainpll_d4 to run at 546MHz 2. Change ethdr_sel source to univpll_d6 to run at 416MHz Signed-off-by: Nancy Lin Change-Id: Ib6518ed6204528489c41e7161534bbd3734ac851 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54082 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8195/pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 6e85def9c2..9e9718eb7a 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -332,8 +332,8 @@ static const struct mux_sel mux_sels[] = { { .id = TOP_SCP_SEL, .sel = 7 }, /* 7: mainpll_d6_d2 */ { .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ /* CLK_CFG_1 */ - { .id = TOP_VPP_SEL, .sel = 2 }, /* 2: mainpll_d5_d2 */ - { .id = TOP_ETHDR_SEL, .sel = 10 }, /* 10: mmpll_d5_d4 */ + { .id = TOP_VPP_SEL, .sel = 9 }, /* 9: mainpll_d4 */ + { .id = TOP_ETHDR_SEL, .sel = 8 }, /* 8: univpll_d6 */ { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ { .id = TOP_CAM_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ /* CLK_CFG_2 */ -- cgit v1.2.3