From a1b3547f0f6e08ad2c83c0224e375217bf187120 Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Fri, 11 Dec 2015 18:13:02 +0530 Subject: intel/skylake: Fix issues found by klockwork src/soc/intel/skylake/acpi.c Function cbmem_find may return NULL, check before using its result. src/soc/intel/skylake/flash_controller.c Remove dead code: spi_claim_bus is a no-op, always returning 0. src/soc/intel/skylake/gpio.c Check for NULL before using pointers. src/soc/intel/skylake/igd.c Don't copy 0-termination of signature string. src/soc/intel/skylake/lpc.c Don't check unsigned >= 0. src/soc/intel/skylake/systemagent.c Explicitly cast result to 64bit. BRANCH=None BUG=chrome-os-partner:48542 TEST=Built & booted Kunimitsu board. Change-Id: I6cbf4f78382383d3c8c3b15f66c5898ab5bf183a Signed-off-by: Patrick Georgi Original-Commit-Id: d98a8cdd3d095a6943c0e104cd4938639a62bd14 Original-Change-Id: Id2a31402618f4c9f6f53525ebcf6b71fd67428db Original-Signed-off-by: Naresh G Solanki Original-Reviewed-on: https://chromium-review.googlesource.com/317522 Original-Commit-Ready: Naresh Solanki Original-Tested-by: Naresh Solanki Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/12991 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/acpi.c | 6 +++++- src/soc/intel/skylake/flash_controller.c | 5 ----- src/soc/intel/skylake/gpio.c | 6 +++++- src/soc/intel/skylake/igd.c | 2 +- src/soc/intel/skylake/lpc.c | 9 ++++++--- src/soc/intel/skylake/systemagent.c | 2 +- 6 files changed, 18 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 4892656b89..c01066f7fb 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -573,11 +573,15 @@ void southcluster_inject_dsdt(device_t device) /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; int i; + ps = cbmem_find(CBMEM_ID_POWER_STATE); + if (ps == NULL) + return -1; + /* PM1_EN state is lost in Deep S3 so enable basic wake events */ pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS; *pm1 = ps->pm1_sts & pm1_en; diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index aca22a9cea..25562a5e9a 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -191,11 +191,6 @@ int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) } flash->spi->rw = SPI_WRITE_FLAG; - ret = spi_claim_bus(flash->spi); - if (ret) { - printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); - return ret; - } start = offset; end = start + len; diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 64b3dda334..db4b8c3ce6 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -261,6 +261,9 @@ static void gpio_handle_pad_mode(const struct pad_config *cfg) bit = 0; hostsw_own_reg = gpio_hostsw_reg(cfg->pad, &bit); + if (hostsw_own_reg == NULL) + return; + reg = read32(hostsw_own_reg); reg &= ~(1U << bit); @@ -282,7 +285,8 @@ static void gpi_enable_smi(gpio_t pad) uint32_t pad_mask; comm = gpio_get_community(pad); - + if (comm == NULL) + return; regs = pcr_port_regs(comm->port_id); gpi_status_reg = (void *)®s[GPI_SMI_STS_OFFSET]; gpi_en_reg = (void *)®s[GPI_SMI_EN_OFFSET]; diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index 9268c095f5..b87467f4a5 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -118,7 +118,7 @@ static int init_igd_opregion(igd_opregion_t *opregion) die("vbt data not found"); memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(IGD_OPREGION_SIGNATURE)); + sizeof(IGD_OPREGION_SIGNATURE) - 1); memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32)); memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index ff413f49ba..e47026c4f8 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -209,9 +209,12 @@ static inline int pch_io_range_in_default(u16 base, u16 size) if (base >= LPC_DEFAULT_IO_RANGE_UPPER) return 0; - /* Is it entirely contained? */ - if (base >= LPC_DEFAULT_IO_RANGE_LOWER && - (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) + /* + * Is it entirely contained? + * Since LPC_DEFAULT_IO_RANGE_LOWER is Zero, + * it need not be checked against lower base. + */ + if ((base + size) < LPC_DEFAULT_IO_RANGE_UPPER) return 1; /* This will return not in range for partial overlaps. */ diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index ff65731e98..ed02f44092 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -183,7 +183,7 @@ static void read_map_entry(device_t dev, struct map_entry *entry, value <<= 32; } - value |= pci_read_config32(dev, entry->reg); + value |= (uint64_t) pci_read_config32(dev, entry->reg); value &= mask; if (entry->is_limit) -- cgit v1.2.3