From 9eb7070bc46c8ce38f3356ec60562c66b576e274 Mon Sep 17 00:00:00 2001
From: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Date: Thu, 2 Dec 2021 10:30:26 +0530
Subject: soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake

Check the Alderlake CPU ID to determine if cse sub-paritition update is
required or not.

BUG=b:202143532

Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/soc/intel/alderlake/romstage/romstage.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src')

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index d33d21f1aa..b9d08c8386 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -15,6 +15,7 @@
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <cpu/intel/cpu_ids.h>
 #include <string.h>
 
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
@@ -23,6 +24,11 @@
 	0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23	\
 }
 
+bool skip_cse_sub_part_update(void)
+{
+	return cpu_get_cpuid() != CPUID_ALDERLAKE_A2;
+}
+
 /* Save the DIMM information for SMBIOS table 17 */
 static void save_dimm_info(void)
 {
-- 
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