From 9cce83c58e3ad6f1b9a8f29f3c6831c696cb5622 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Thu, 3 Dec 2020 18:47:04 +0800 Subject: mb/google/volteer/var/voxel: Update DPTF parameters remove TCC offset setting in overridetree.cb, use default setting(# TCC of 90) in baseboard. BUG=b:174547185 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264 Reviewed-by: Sumeet R Pawnikar Reviewed-by: David Wu Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/voxel/overridetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 9c4aa47d2f..2dd15669fe 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" - register "tcc_offset" = "5" # TCC of 95 register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 18, -- cgit v1.2.3