From 9abeb9c0626244e5f889536bbc9de0bf685eb922 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 15 Sep 2021 16:40:35 +0200 Subject: soc/intel/tgl: correct wrong gpio GPI enable register base offset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reference: Intel doc# 631120-001. Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Nico Huber --- src/soc/intel/tigerlake/include/soc/gpio_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index c90931d80c..2f404393a0 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -289,7 +289,7 @@ #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xb0 #define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x110 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define GPI_NMI_STS_0 0x1c0 -- cgit v1.2.3