From 99d8818af332f4db8ded058c7e5e59e2f56f7bc9 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 14 Nov 2013 11:06:17 -0600 Subject: baytrail: don't allow PCIE wake ups The PCIe subsystem was constantly waking up boards from S3 and S5. Completely disable PCIe wake ups. It can be made mainboard-configurable later if needed. BUG=chrome-os-partner:24004 BRANCH=None TEST=Both S3 and EC RW->RW update (trip through S5) don't cause wakeups. Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/176791 Reviewed-by: Shawn Nematbakhsh Reviewed-on: http://review.coreboot.org/4972 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/smm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index c654c8597e..e10c70b699 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -93,8 +93,8 @@ void southcluster_smm_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events */ - enable_pm1(PWRBTN_EN | GBL_EN); + /* Configure events Disable pcie wake. */ + enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ -- cgit v1.2.3