From 97bc693abc482139774a656212935387d43df8e2 Mon Sep 17 00:00:00 2001 From: Rishika Raj Date: Mon, 29 Jul 2024 08:03:01 +0000 Subject: mb/google/brya/var/orisa: Remove redundant defaults from overridetree Streamline variant-level overrides by removing redundant entries that already exist in either the SoC-level or the platform-level configurations. BUG=None TEST=emerge-nissa coreboot Change-Id: I0b28354dfb865900a78a9d0738e00aa952eade0e Signed-off-by: Rishika Raj Reviewed-on: https://review.coreboot.org/c/coreboot/+/83674 Tested-by: build bot (Jenkins) Reviewed-by: Dinesh Gehlot Reviewed-by: Subrata Banik Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/orisa/overridetree.cb | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 543a66771a..92909ab425 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -86,10 +86,7 @@ chip soc/intel/alderlake register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 @@ -511,7 +508,6 @@ chip soc/intel/alderlake end end #I2C5 device ref heci1 on end - device ref pcie_rp7 off end device ref emmc on probe STORAGE STORAGE_UNKNOWN probe STORAGE STORAGE_EMMC -- cgit v1.2.3