From 93d9517795b58fca2639bc66e359a61219e82b81 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 22 Jul 2020 17:30:49 +0200 Subject: nb/intel/ironlake: Add definition for QPI Link PCI device On multi-socket platforms, there can be two QPI buses, each with its own PCI device. We only have one QPI link on Arrandale, though. In case support for multi-socket processors ever gets added, name it Link 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/ironlake/ironlake.h | 5 +++++ src/northbridge/intel/ironlake/raminit.c | 10 +++++----- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index fa59565ba8..bd42f21006 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -60,6 +60,11 @@ #define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ #define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ +/* + * QPI Link 0 + */ +#define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) + /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f8f6b74466..2c475694d4 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3950,11 +3950,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR8_OR(0x2ca8, 1); // guess } - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000); - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555); - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! + pci_read_config32(QPI_LINK_0, 0x048); // !!!! + pci_write_config32(QPI_LINK_0, 0x048, 0x140000); + pci_read_config32(QPI_LINK_0, 0x058); // !!!! + pci_write_config32(QPI_LINK_0, 0x058, 0x64555); + pci_read_config32(QPI_LINK_0, 0x058); // !!!! pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); gav(MCHBAR32(0x1af0)); // !!!! -- cgit v1.2.3