From 93cb1809a2034aa398ad0cb5faf7d5e8e48bfe44 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Thu, 28 Jan 2021 12:20:42 +0100
Subject: cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZE

This fixes a regression introduced by
Commit 985821c (cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE)
where the CAR base is not aligned to its size.

Change-Id: If54cb178e86426e1491dda4047302632d876a8f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50029
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/socket_LGA775/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 537a0d1c5f..3ce106a394 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -25,6 +25,6 @@ config DCACHE_BSP_STACK_SIZE
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE
+	default 0xfeff8000 # 4GB - 16MB - DCACHE_RAM_SIZE
 
 endif # CPU_INTEL_SOCKET_LGA775
-- 
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