From 93643e362d541b6ab32147e5886ca661a9eec1ac Mon Sep 17 00:00:00 2001 From: Philipp Deppenwiese Date: Fri, 17 Oct 2014 16:10:32 +0200 Subject: Fix ICH spi implementation which reads data from different chips. This patch adjusts the read timeout in order to support flash chips which needs more than 60ms to complete a spi command. This problem can be reproduced on a Thinkpad T520 with M25PX64 spi chip ( suspend to ram bug ). Change-Id: I22b2e59f1855ead6162a292b83b9b854b55c0235 Signed-off-by: Philipp Deppenwiese Reviewed-on: http://review.coreboot.org/7105 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Vladimir Serbinenko --- src/southbridge/intel/common/spi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 8e7192b49f..2ea9a24142 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -517,7 +517,7 @@ static int spi_setup_offset(spi_transaction *trans) } /* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set * below is True) or 0. In case the wait was for the bit(s) to set - write * those bits back, which would cause resetting them. * @@ -525,7 +525,7 @@ static int spi_setup_offset(spi_transaction *trans) */ static int ich_status_poll(u16 bitmask, int wait_til_set) { - int timeout = 6000; /* This will result in 60 ms */ + int timeout = 600000; /* This will result in 6 seconds */ u16 status = 0; while (timeout--) { @@ -538,7 +538,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) udelay(10); } - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n", status, bitmask); return -1; } -- cgit v1.2.3