From 92dc39129156307913dbf3c07f926554f0c14ab8 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 30 Jul 2019 09:53:23 +0800 Subject: soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:138282962 TEST=Ensure that the Interrupt status & enable registers are reset during the boot-up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg --- src/soc/intel/cannonlake/bootblock/bootblock.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 5555969289..30c2266096 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -59,6 +59,11 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); report_platform_info(); pch_early_init(); } -- cgit v1.2.3