From 92712d361d0ecdd33d5fb097630b0b61e96ab5bd Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Fri, 16 Feb 2018 12:44:11 +0100 Subject: soc/nvidia/tegra210: set up the clock of the chosen UART MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't always set up UARTA, but instead honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the chosen UART. Now the matching clock for the used UART is set up. (The UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.) Change-Id: Ife209d42af83459136a019c21c2a069396ab36db Signed-off-by: Andre Heider Reviewed-on: https://review.coreboot.org/23796 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Paul Menzel Reviewed-by: Julius Werner --- src/soc/nvidia/tegra210/clock.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index cc8af55761..ba1efdc000 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -489,12 +490,15 @@ u32 clock_configure_plld(u32 frequency) */ void clock_early_uart(void) { - write32(CLK_RST_REG(clk_src_uarta), - CLK_SRC_DEV_ID(UARTA, PLLP) << CLK_SOURCE_SHIFT | + if (console_uart_get_id() == UART_ID_NONE) + return; + + write32(console_uart_clk_rst_reg(), + console_uart_clk_src_dev_id() << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_PLLP_KHZ, 1843)); - clock_enable_clear_reset_l(CLK_L_UARTA); + console_uart_clock_enable_clear_reset(); } /* Enable output clock (CLK1~3) for external peripherals. */ -- cgit v1.2.3