From 91b80416b700bbc40f282ba090b1f43d822f36fc Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 27 Sep 2017 16:44:40 -0600 Subject: amd/stoneyridge: Enable SMI trap on SlpTyp Program PMx08 to support SMIs when software writes the SlpTyp bit in the Pm1Control register. The southbridge needs to send the SMI message prior to the completion response of the I/O cycle. Also, disable sending the STPCLK message before the completion response. Disable the SlpTyp functionality, then enable the SMI source. BUG=b:65595850 Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/21752 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/southbridge.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src') diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 6ab06780c8..600b064f2d 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -42,6 +42,8 @@ void sb_enable(device_t dev) static void sb_init_acpi_ports(void) { + u32 reg; + /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. */ @@ -57,6 +59,22 @@ static void sb_init_acpi_ports(void) /* APMC - SMI Command Port */ pm_write16(PM_ACPI_SMI_CMD, APM_CNT); configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); + + /* SMI on SlpTyp requires sending SMI before completion + * response of the I/O write. The BKDG also specifies + * clearing ForceStpClkRetry for SMI trapping. + */ + reg = pm_read32(PM_PCI_CTRL); + reg |= FORCE_SLPSTATE_RETRY; + reg &= ~FORCE_STPCLK_RETRY; + pm_write32(PM_PCI_CTRL, reg); + + /* Disable SlpTyp feature */ + reg = pm_read8(PM_RST_CTRL1); + reg &= ~SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, reg); + + configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); } else { pm_write16(PM_ACPI_SMI_CMD, 0); } -- cgit v1.2.3