From 8f08f5f5c71d7214b5bdd40f298177205e663a96 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@chromium.org>
Date: Sun, 24 Sep 2017 20:50:14 -0700
Subject: soraka: Ensure I2C5 frequency is less than 400kHz

Update I2C5 bus parameters to obtain clock frequency <400kHz.

BUG=b:65062416
TEST=Verified using an oscilloscope that I2C5 bus frequency
in factory is ~397kHz.

Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/google/poppy/variants/soraka/devicetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index fa16ae02e5..6d4e8a5665 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -226,8 +226,8 @@ chip soc/intel/skylake
 		.speed = I2C_SPEED_FAST,
 		.speed_config[0] = {
 			.speed = I2C_SPEED_FAST,
-			.scl_lcnt = 180,
-			.scl_hcnt = 80,
+			.scl_lcnt = 195,
+			.scl_hcnt = 90,
 			.sda_hold = 36,
 		},
 	}"
-- 
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