From 8ee11b3e09df4fb6d9cd4fb84e6268e39822728e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 27 Jun 2021 21:08:32 +0300 Subject: nb/intel: Drop local legacy_hole definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are architectural and followup works will address the VGA MMIO and/or ASEG better. Change-Id: I88e1dca8058661e31ba934b9860751e13a107108 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55928 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/ironlake/northbridge.c | 5 ++--- src/northbridge/intel/pineview/northbridge.c | 5 ++--- src/northbridge/intel/sandybridge/northbridge.c | 12 ++++-------- src/northbridge/intel/x4x/northbridge.c | 10 +++------- 4 files changed, 11 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index d2f5c79fe1..aec0fc0b31 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -33,7 +33,6 @@ int bridge_silicon_revision(void) * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ -static const int legacy_hole_base_k = 0xa0000 / 1024; static void add_fixed_resources(struct device *dev, int index) { @@ -54,8 +53,8 @@ static void add_fixed_resources(struct device *dev, int index) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k); - reserved_ram_resource_kb(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB); + mmio_from_to(dev, index++, 0xa0000, 0xc0000); + reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); } #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 4a5a91823d..bfef56e4c4 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -20,7 +20,6 @@ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ -static const int legacy_hole_base_k = 0xa0000 / KiB; static void add_fixed_resources(struct device *dev, int index) { @@ -35,8 +34,8 @@ static void add_fixed_resources(struct device *dev, int index) | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k); - reserved_ram_resource_kb(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB); + mmio_from_to(dev, index++, 0xa0000, 0xc0000); + reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); } static void mch_domain_read_resources(struct device *dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 032e500dc3..51e7847788 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -35,8 +35,6 @@ bool is_sandybridge(void) * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; static const char *northbridge_acpi_name(const struct device *dev) { @@ -66,9 +64,8 @@ static void add_fixed_resources(struct device *dev, int index) { mmio_resource_kb(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); - mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); - - reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); + mmio_from_to(dev, index++, 0xa0000, 0xc0000); + reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); if (is_sandybridge()) { /* Required for SandyBridge sighting 3715511 */ @@ -207,9 +204,8 @@ static void mc_read_resources(struct device *dev) printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); /* Report the memory regions */ - ram_resource_kb(dev, index++, 0, legacy_hole_base_k); - ram_resource_kb(dev, index++, legacy_hole_base_k + legacy_hole_size_k, - (tomk - (legacy_hole_base_k + legacy_hole_size_k))); + ram_from_to(dev, index++, 0, 0xa0000); + ram_from_to(dev, index++, 1 * MiB, tomk * KiB); /* * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM. diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 8a104a811a..035862d499 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -13,8 +13,6 @@ #include #include -static const int legacy_hole_base_k = 0xa0000 / 1024; - static void mch_domain_read_resources(struct device *dev) { u8 index; @@ -81,11 +79,9 @@ static void mch_domain_read_resources(struct device *dev) printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); /* Report the memory regions */ - ram_resource_kb(dev, index++, 0, legacy_hole_base_k); - mmio_resource_kb(dev, index++, legacy_hole_base_k, - (0xc0000 >> 10) - legacy_hole_base_k); - reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, - (0x100000 - 0xc0000) >> 10); + ram_from_to(dev, index++, 0, 0xa0000); + mmio_from_to(dev, index++, 0xa0000, 0xc0000); + reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); ram_resource_kb(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10))); /* -- cgit v1.2.3