From 8d3c4d1bb39fa354df59abf55b37fc694a2cb7c9 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 6 Jul 2016 23:16:01 -0500 Subject: mainboard/google/reef: apply EVT board changes Based on the board revision apply the correct GPIO changes. The only differences are the addition of 2 peripheral wake signals and a dedicated peripheral reset line. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15562 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- src/mainboard/google/reef/gpio.h | 16 +++++++++++++--- src/mainboard/google/reef/mainboard.c | 15 +++++++++++++++ 2 files changed, 28 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 14cf880cfd..cbad4c6b58 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -274,7 +274,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), - PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), @@ -287,7 +286,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */ - PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_18, NONE, DEEP, LEVEL, NONE), /* Trackpad IRQ */ @@ -319,7 +317,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ - PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ @@ -356,5 +353,18 @@ static const struct pad_config early_gpio_table[] = { #define MEM_CONFIG1 GPIO_102 #define MEM_CONFIG0 GPIO_101 +static const struct pad_config proto_diff_table[] = { + PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ +}; + +/* Wake peripheral signals post proto. */ +static const struct pad_config nonproto_diff_table[] = { + PAD_CFG_GPI_SCI(GPIO_3, UP_20K, DEEP, LEVEL, NONE), /* FP_INT_L */ + PAD_CFG_GPI_SCI(GPIO_15, NONE, DEEP, LEVEL, NONE), /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ +}; + #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 2b121ef4b3..def6900cf0 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -24,7 +25,21 @@ static void mainboard_init(void *chip_info) { + int boardid; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* Apply proto board settings if board matches. */ + if (boardid == 0) + gpio_configure_pads(proto_diff_table, + ARRAY_SIZE(proto_diff_table)); + else + gpio_configure_pads(nonproto_diff_table, + ARRAY_SIZE(nonproto_diff_table)); + mainboard_ec_init(); } -- cgit v1.2.3