From 8ce14a794825a09557e69d759049e03d7724f09e Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 29 Mar 2016 12:30:38 +0530 Subject: soc/qualcomm/ipq40xx: Return NULL for cbmem_top if DRAM is not initialized DRAM initialization on gale requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. BUG=chrome-os-partner:49249 TEST=Able to compile and boot to depthcharge. Doesn't crash in imd_handle_init_partial_recovery BRANCH=none Change-Id: Iaac24252ee4fb9f59d767730bf9dd68baa42a68f Signed-off-by: Patrick Georgi Original-Commit-Id: 4849c15dee2d3782ede4ee4157e432bd4d5602f0 Original-Change-Id: I3722b7ab5a6585a250138c828eb3d7919b0c1178 Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/335425 Original-Commit-Ready: David Hendricks Original-Reviewed-by: David Hendricks Reviewed-on: https://review.coreboot.org/14660 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/gale/mmu.c | 3 +++ src/soc/qualcomm/ipq40xx/Makefile.inc | 1 + src/soc/qualcomm/ipq40xx/cbmem.c | 16 ++++++++++++++++ src/soc/qualcomm/ipq40xx/include/soc/soc_services.h | 3 +++ 4 files changed, 23 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index 65797e7463..6c096a5bf4 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -12,6 +12,7 @@ #include #include +#include #include "mmu.h" #define WIFI_IMEM_0_START ((uintptr_t)_wifi_imem_0 / KiB) @@ -33,6 +34,8 @@ void setup_dram_mappings(enum dram_state dram) mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 07ca023e0b..9cf96cfedb 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_SOC_QC_IPQ40XX),y) bootblock-y += clock.c +bootblock-y += cbmem.c bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 7aff231be7..05325cceb9 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -16,7 +16,23 @@ #include #include +static int cbmem_backing_store_ready; + +void ipq_cbmem_backing_store_ready(void) +{ + cbmem_backing_store_ready = 1; +} + void *cbmem_top(void) { + /* + * In romstage, make sure that cbmem backing store is ready before + * returning pointer to cbmem top. Otherwise, it could lead to issues + * with components that utilize cbmem in romstage (e.g. vboot_locator + * for loading ipq blobs before DRAM is initialized). + */ + if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + return NULL; + return _memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h b/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h index 5ad11f1a10..98147cf656 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/soc_services.h @@ -32,4 +32,7 @@ int tz_init_wrapper(int, int, void *); /* Load RPM code into memory and trigger its execution. */ void start_rpm(void); +/* Mark cbmem backing store as ready. */ +void ipq_cbmem_backing_store_ready(void); + #endif -- cgit v1.2.3