From 8c70dd66da02f4ee46086f0bdc54b56e39c7054f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 5 Jan 2019 17:20:11 +0100 Subject: cpu/intel/microcode_asm.S: Fix reading cpuid(1) and checking PF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The value of %ebx was clobbered later on by a cpuid call. A bitwise and needs to be used to check processor flags. Change-Id: I29f1fddfe3cc2cbfc7c843b6aff7425f32e12317 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30680 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/intel/microcode/microcode_asm.S | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 039e02a2b7..319785d2de 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -88,11 +88,6 @@ update_bsp_microcode: * Current installed microcode revision -> %edx */ - /* Processor family+model signature=cpuid_eax(1) */ - movl $1, %eax - cpuid - movl %eax, %ebx - /* Processor flags * rdmsr 0x17 * pf = 1 << ((msr.hi >> 18) & 7) */ @@ -113,6 +108,10 @@ update_bsp_microcode: wrmsr movl $0x1, %eax cpuid + + /* Processor family+model signature=cpuid_eax(1) */ + movl %eax, %ebx + movl $IA32_BIOS_SIGN_ID, %ecx rdmsr @@ -126,8 +125,8 @@ check_microcode_entry: jne next_entry /* Processor flags */ - cmpl PROCESSOR_FLAG(%esi), %ebp - jne next_entry + test PROCESSOR_FLAG(%esi), %ebp + jz next_entry /* Check if revision is higher than current */ cmpl UPDATE_VER_OFFSET(%esi), %edx -- cgit v1.2.3