From 8b122600c4689e05b5fb94c7559a734596f54fdd Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 18 Jan 2024 13:05:06 -0700 Subject: southbridge: Rename Makefiles from .inc to .mk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth Change-Id: Ic80d27a963da8eddc3d1f0d9a3d59763028d4ed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80075 Reviewed-by: Felix Singer Reviewed-by: Maximilian Brune Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/southbridge/amd/common/Makefile.inc | 3 - src/southbridge/amd/common/Makefile.mk | 3 + src/southbridge/amd/pi/Makefile.inc | 4 - src/southbridge/amd/pi/Makefile.mk | 4 + src/southbridge/amd/pi/hudson/Makefile.inc | 145 --------------------- src/southbridge/amd/pi/hudson/Makefile.mk | 145 +++++++++++++++++++++ src/southbridge/intel/bd82x6x/Makefile.inc | 43 ------ src/southbridge/intel/bd82x6x/Makefile.mk | 43 ++++++ src/southbridge/intel/common/Makefile.inc | 55 -------- src/southbridge/intel/common/Makefile.mk | 55 ++++++++ src/southbridge/intel/common/firmware/Makefile.inc | 138 -------------------- src/southbridge/intel/common/firmware/Makefile.mk | 138 ++++++++++++++++++++ src/southbridge/intel/i82371eb/Makefile.inc | 19 --- src/southbridge/intel/i82371eb/Makefile.mk | 19 +++ src/southbridge/intel/i82801dx/Makefile.inc | 20 --- src/southbridge/intel/i82801dx/Makefile.mk | 20 +++ src/southbridge/intel/i82801gx/Makefile.inc | 28 ---- src/southbridge/intel/i82801gx/Makefile.mk | 28 ++++ src/southbridge/intel/i82801ix/Makefile.inc | 27 ---- src/southbridge/intel/i82801ix/Makefile.mk | 27 ++++ src/southbridge/intel/i82801jx/Makefile.inc | 24 ---- src/southbridge/intel/i82801jx/Makefile.mk | 24 ++++ src/southbridge/intel/i82870/Makefile.inc | 8 -- src/southbridge/intel/i82870/Makefile.mk | 8 ++ src/southbridge/intel/ibexpeak/Makefile.inc | 35 ----- src/southbridge/intel/ibexpeak/Makefile.mk | 35 +++++ src/southbridge/intel/lynxpoint/Makefile.inc | 60 --------- src/southbridge/intel/lynxpoint/Makefile.mk | 60 +++++++++ src/southbridge/intel/lynxpoint/hsio/Makefile.inc | 8 -- src/southbridge/intel/lynxpoint/hsio/Makefile.mk | 8 ++ src/southbridge/ricoh/rl5c476/Makefile.inc | 7 - src/southbridge/ricoh/rl5c476/Makefile.mk | 7 + src/southbridge/ti/pci1x2x/Makefile.inc | 7 - src/southbridge/ti/pci1x2x/Makefile.mk | 7 + src/southbridge/ti/pci7420/Makefile.inc | 8 -- src/southbridge/ti/pci7420/Makefile.mk | 8 ++ src/southbridge/ti/pcixx12/Makefile.inc | 7 - src/southbridge/ti/pcixx12/Makefile.mk | 7 + 38 files changed, 646 insertions(+), 646 deletions(-) delete mode 100644 src/southbridge/amd/common/Makefile.inc create mode 100644 src/southbridge/amd/common/Makefile.mk delete mode 100644 src/southbridge/amd/pi/Makefile.inc create mode 100644 src/southbridge/amd/pi/Makefile.mk delete mode 100644 src/southbridge/amd/pi/hudson/Makefile.inc create mode 100644 src/southbridge/amd/pi/hudson/Makefile.mk delete mode 100644 src/southbridge/intel/bd82x6x/Makefile.inc create mode 100644 src/southbridge/intel/bd82x6x/Makefile.mk delete mode 100644 src/southbridge/intel/common/Makefile.inc create mode 100644 src/southbridge/intel/common/Makefile.mk delete mode 100644 src/southbridge/intel/common/firmware/Makefile.inc create mode 100644 src/southbridge/intel/common/firmware/Makefile.mk delete mode 100644 src/southbridge/intel/i82371eb/Makefile.inc create mode 100644 src/southbridge/intel/i82371eb/Makefile.mk delete mode 100644 src/southbridge/intel/i82801dx/Makefile.inc create mode 100644 src/southbridge/intel/i82801dx/Makefile.mk delete mode 100644 src/southbridge/intel/i82801gx/Makefile.inc create mode 100644 src/southbridge/intel/i82801gx/Makefile.mk delete mode 100644 src/southbridge/intel/i82801ix/Makefile.inc create mode 100644 src/southbridge/intel/i82801ix/Makefile.mk delete mode 100644 src/southbridge/intel/i82801jx/Makefile.inc create mode 100644 src/southbridge/intel/i82801jx/Makefile.mk delete mode 100644 src/southbridge/intel/i82870/Makefile.inc create mode 100644 src/southbridge/intel/i82870/Makefile.mk delete mode 100644 src/southbridge/intel/ibexpeak/Makefile.inc create mode 100644 src/southbridge/intel/ibexpeak/Makefile.mk delete mode 100644 src/southbridge/intel/lynxpoint/Makefile.inc create mode 100644 src/southbridge/intel/lynxpoint/Makefile.mk delete mode 100644 src/southbridge/intel/lynxpoint/hsio/Makefile.inc create mode 100644 src/southbridge/intel/lynxpoint/hsio/Makefile.mk delete mode 100644 src/southbridge/ricoh/rl5c476/Makefile.inc create mode 100644 src/southbridge/ricoh/rl5c476/Makefile.mk delete mode 100644 src/southbridge/ti/pci1x2x/Makefile.inc create mode 100644 src/southbridge/ti/pci1x2x/Makefile.mk delete mode 100644 src/southbridge/ti/pci7420/Makefile.inc create mode 100644 src/southbridge/ti/pci7420/Makefile.mk delete mode 100644 src/southbridge/ti/pcixx12/Makefile.inc create mode 100644 src/southbridge/ti/pcixx12/Makefile.mk (limited to 'src') diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc deleted file mode 100644 index ce8b3d41b5..0000000000 --- a/src/southbridge/amd/common/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c diff --git a/src/southbridge/amd/common/Makefile.mk b/src/southbridge/amd/common/Makefile.mk new file mode 100644 index 0000000000..ce8b3d41b5 --- /dev/null +++ b/src/southbridge/amd/common/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c diff --git a/src/southbridge/amd/pi/Makefile.inc b/src/southbridge/amd/pi/Makefile.inc deleted file mode 100644 index ed4247da1a..0000000000 --- a/src/southbridge/amd/pi/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += hudson diff --git a/src/southbridge/amd/pi/Makefile.mk b/src/southbridge/amd/pi/Makefile.mk new file mode 100644 index 0000000000..ed4247da1a --- /dev/null +++ b/src/southbridge/amd/pi/Makefile.mk @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += hudson diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc deleted file mode 100644 index e7ec1b73ec..0000000000 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ /dev/null @@ -1,145 +0,0 @@ -## SPDX-License-Identifier: BSD-3-Clause - -# Copyright (c) 2012, Advanced Micro Devices, Inc. -# 2013 - 2014, Sage Electronic Engineering, LLC - -bootblock-y += bootblock.c -bootblock-y += early_setup.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c - -romstage-y += early_setup.c -romstage-y += enable_usbdebug.c -romstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c -romstage-y += smbus.c -romstage-y += smbus_spd.c - -verstage-y += early_setup.c - -ramstage-y += enable_usbdebug.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -ramstage-y += hda.c -ramstage-y += hudson.c -ramstage-y += ide.c -ramstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c -ramstage-y += lpc.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += sata.c -ramstage-y += sd.c -ramstage-y += sm.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -ramstage-y += usb.c - -all-y += reset.c - -smm-y += smihandler.c -smm-y += smi_util.c - -CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include - -# ROMSIG At ROMBASE + 0x20000: -# +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | -# +-----------+---------------+----------------+------------+ -# |PSPDIR ADDR| -# +-----------+ -# -# EC ROM should be 64K aligned. - -ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) -else -HUDSON_FWM_POSITION=0xfff20000 -endif - -ifeq ($(CONFIG_HUDSON_PSP), y) - -ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -FIRMWARE_TYPE= - -endif - -#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key -#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin -#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key - -endif - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) -OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) -OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec) - -OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) -OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) -OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) -OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) -OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) -OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) -OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) -OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) -OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) - -$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(call strip_quotes, $(AMD_PUBKEY2_FILE)) \ - $(call strip_quotes, $(PUBSIGNEDKEY2_FILE)) \ - $(call strip_quotes, $(PSPBTLDR2_FILE)) \ - $(call strip_quotes, $(SMUFWM2_FILE)) \ - $(call strip_quotes, $(SMUFWM2_FN_FILE)) \ - $(call strip_quotes, $(PSPRCVR2_FILE)) \ - $(call strip_quotes, $(PSPSECUREOS2_FILE)) \ - $(call strip_quotes, $(PSPNVRAM2_FILE)) \ - $(call strip_quotes, $(SMUSCS2_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG2_FILE)) \ - $(call strip_quotes, $(PSPTRUSTLETS2_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY2_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_2_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_2_FN_FILE)) \ - $(DEP_FILES) \ - $(AMDFWTOOL) - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(OPT_HUDSON_XHCI_FWM_FILE) \ - $(OPT_HUDSON_IMC_FWM_FILE) \ - $(OPT_HUDSON_GEC_FWM_FILE) \ - $(OPT_2AMD_PUBKEY_FILE) \ - $(OPT_2PSPBTLDR_FILE) \ - $(OPT_2SMUFWM_FILE) \ - $(OPT_2SMUFWM_FN_FILE) \ - $(OPT_2PSPRCVR_FILE) \ - $(OPT_2PUBSIGNEDKEY_FILE) \ - $(OPT_2PSPSECUREOS_FILE) \ - $(OPT_2PSPNVRAM_FILE) \ - $(OPT_2PSPSECUREDEBUG_FILE) \ - $(OPT_2PSPTRUSTLETS_FILE) \ - $(OPT_2TRUSTLETKEY_FILE) \ - $(OPT_2SMUFIRMWARE2_FILE) \ - $(OPT_2SMUFIRMWARE2_FN_FILE) \ - $(OPT_2SMUSCS_FILE) \ - --flashsize $(CONFIG_ROM_SIZE) \ - --location $(HUDSON_FWM_POSITION) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --output $@ - -ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) - printf " DD Adding AMD Firmware\n" - dd if=$(obj)/amdfw.rom \ - of=$< conv=notrunc bs=1 seek=131072 >/dev/null 2>&1 - -else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) - -cbfs-files-y += apu/amdfw -apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(HUDSON_FWM_POSITION) -apu/amdfw-type := raw - -endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/southbridge/amd/pi/hudson/Makefile.mk b/src/southbridge/amd/pi/hudson/Makefile.mk new file mode 100644 index 0000000000..e7ec1b73ec --- /dev/null +++ b/src/southbridge/amd/pi/hudson/Makefile.mk @@ -0,0 +1,145 @@ +## SPDX-License-Identifier: BSD-3-Clause + +# Copyright (c) 2012, Advanced Micro Devices, Inc. +# 2013 - 2014, Sage Electronic Engineering, LLC + +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +romstage-y += early_setup.c +romstage-y += enable_usbdebug.c +romstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c +romstage-y += smbus.c +romstage-y += smbus_spd.c + +verstage-y += early_setup.c + +ramstage-y += enable_usbdebug.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-y += hda.c +ramstage-y += hudson.c +ramstage-y += ide.c +ramstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += sd.c +ramstage-y += sm.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += usb.c + +all-y += reset.c + +smm-y += smihandler.c +smm-y += smi_util.c + +CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include + +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# |PSPDIR ADDR| +# +-----------+ +# +# EC ROM should be 64K aligned. + +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) +else +HUDSON_FWM_POSITION=0xfff20000 +endif + +ifeq ($(CONFIG_HUDSON_PSP), y) + +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) +FIRMWARE_TYPE= + +endif + +#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key +#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin +#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key + +endif + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) +OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) +OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILEddd), --gec) + +OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) +OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) +OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) +OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) +OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) +OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) +OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) +OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) +OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) +OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) +OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) +OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) + +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ + $(call strip_quotes, $(AMD_PUBKEY2_FILE)) \ + $(call strip_quotes, $(PUBSIGNEDKEY2_FILE)) \ + $(call strip_quotes, $(PSPBTLDR2_FILE)) \ + $(call strip_quotes, $(SMUFWM2_FILE)) \ + $(call strip_quotes, $(SMUFWM2_FN_FILE)) \ + $(call strip_quotes, $(PSPRCVR2_FILE)) \ + $(call strip_quotes, $(PSPSECUREOS2_FILE)) \ + $(call strip_quotes, $(PSPNVRAM2_FILE)) \ + $(call strip_quotes, $(SMUSCS2_FILE)) \ + $(call strip_quotes, $(PSPSECUREDEBUG2_FILE)) \ + $(call strip_quotes, $(PSPTRUSTLETS2_FILE)) \ + $(call strip_quotes, $(TRUSTLETKEY2_FILE)) \ + $(call strip_quotes, $(SMUFIRMWARE2_2_FILE)) \ + $(call strip_quotes, $(SMUFIRMWARE2_2_FN_FILE)) \ + $(DEP_FILES) \ + $(AMDFWTOOL) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(OPT_HUDSON_XHCI_FWM_FILE) \ + $(OPT_HUDSON_IMC_FWM_FILE) \ + $(OPT_HUDSON_GEC_FWM_FILE) \ + $(OPT_2AMD_PUBKEY_FILE) \ + $(OPT_2PSPBTLDR_FILE) \ + $(OPT_2SMUFWM_FILE) \ + $(OPT_2SMUFWM_FN_FILE) \ + $(OPT_2PSPRCVR_FILE) \ + $(OPT_2PUBSIGNEDKEY_FILE) \ + $(OPT_2PSPSECUREOS_FILE) \ + $(OPT_2PSPNVRAM_FILE) \ + $(OPT_2PSPSECUREDEBUG_FILE) \ + $(OPT_2PSPTRUSTLETS_FILE) \ + $(OPT_2TRUSTLETKEY_FILE) \ + $(OPT_2SMUFIRMWARE2_FILE) \ + $(OPT_2SMUFIRMWARE2_FN_FILE) \ + $(OPT_2SMUSCS_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) \ + --location $(HUDSON_FWM_POSITION) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --output $@ + +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) + printf " DD Adding AMD Firmware\n" + dd if=$(obj)/amdfw.rom \ + of=$< conv=notrunc bs=1 seek=131072 >/dev/null 2>&1 + +else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(HUDSON_FWM_POSITION) +apu/amdfw-type := raw + +endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc deleted file mode 100644 index 32fddc4742..0000000000 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ /dev/null @@ -1,43 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y) - -bootblock-y += bootblock.c -bootblock-y += early_pch.c - -ramstage-y += pch.c -ramstage-y += azalia.c -ramstage-y += common.c -ramstage-y += fadt.c -ramstage-y += lpc.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += sata.c -ramstage-y += usb_ehci.c -ramstage-y += usb_xhci.c -ramstage-y += me.c -ramstage-y += me_8.x.c -ramstage-y += me_common.c -ramstage-y += smbus.c -ramstage-y += ../common/pciehp.c - -ramstage-y += me_status.c - -ramstage-$(CONFIG_ELOG) += elog.c - -smm-y += common.c smihandler.c me_smm.c me_common.c - -romstage-y += common.c -romstage-y += me_status.c -romstage-y += early_rcba.c -romstage-y += early_pch.c - -ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) -romstage-y += early_thermal.c early_me.c early_usb.c -else -romstage-y += early_me_mrc.c early_usb_mrc.c -endif - -CPPFLAGS_common += -I$(src)/southbridge/intel/bd82x6x/include - -endif diff --git a/src/southbridge/intel/bd82x6x/Makefile.mk b/src/southbridge/intel/bd82x6x/Makefile.mk new file mode 100644 index 0000000000..32fddc4742 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/Makefile.mk @@ -0,0 +1,43 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y) + +bootblock-y += bootblock.c +bootblock-y += early_pch.c + +ramstage-y += pch.c +ramstage-y += azalia.c +ramstage-y += common.c +ramstage-y += fadt.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += usb_ehci.c +ramstage-y += usb_xhci.c +ramstage-y += me.c +ramstage-y += me_8.x.c +ramstage-y += me_common.c +ramstage-y += smbus.c +ramstage-y += ../common/pciehp.c + +ramstage-y += me_status.c + +ramstage-$(CONFIG_ELOG) += elog.c + +smm-y += common.c smihandler.c me_smm.c me_common.c + +romstage-y += common.c +romstage-y += me_status.c +romstage-y += early_rcba.c +romstage-y += early_pch.c + +ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +romstage-y += early_thermal.c early_me.c early_usb.c +else +romstage-y += early_me_mrc.c early_usb_mrc.c +endif + +CPPFLAGS_common += -I$(src)/southbridge/intel/bd82x6x/include + +endif diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc deleted file mode 100644 index 2f4c777561..0000000000 --- a/src/southbridge/intel/common/Makefile.inc +++ /dev/null @@ -1,55 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -# CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. -subdirs-y += firmware - -all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c - -all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c - -all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME) += me.c - -ifeq ($(CONFIG_CONSOLE_I2C_SMBUS),y) -bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c -endif -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c - -ifeq ($(CONFIG_CONSOLE_I2C_SMBUS),y) -all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c -else -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c -endif -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus_ops.c - -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c - -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c - -all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c -smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c - -bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c - -bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c - -all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -ifeq ($(CONFIG_SPI_FLASH_SMM),y) -smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -endif - -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN) += acpi_pirq_gen.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ) += rcba_pirq.c - -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c -smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c - -smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c - -all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c diff --git a/src/southbridge/intel/common/Makefile.mk b/src/southbridge/intel/common/Makefile.mk new file mode 100644 index 0000000000..2f4c777561 --- /dev/null +++ b/src/southbridge/intel/common/Makefile.mk @@ -0,0 +1,55 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. +subdirs-y += firmware + +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c + +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c + +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME) += me.c + +ifeq ($(CONFIG_CONSOLE_I2C_SMBUS),y) +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c +endif +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c + +ifeq ($(CONFIG_CONSOLE_I2C_SMBUS),y) +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +else +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +endif +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus_ops.c + +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c + +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c + +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c + +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c + +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c + +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +endif + +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN) += acpi_pirq_gen.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ) += rcba_pirq.c + +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c + +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c + +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc deleted file mode 100644 index 1425d5a352..0000000000 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ /dev/null @@ -1,138 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) - -# Run intermediate steps when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS - -ifeq ($(CONFIG_HAVE_IFD_BIN),y) -$(call add_intermediate, add_intel_firmware) -else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) -show_notices:: warn_intel_firmware -endif - -IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) -ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),) -IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET) -endif - -ifeq ($(CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS),y) -IFDTOOL_LOCK_ME_MODE := -lr -else -IFDTOOL_LOCK_ME_MODE := -l -endif - -add_intel_firmware: $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) -ifeq ($(CONFIG_HAVE_ME_BIN),y) - -OBJ_ME_BIN := $(obj)/me.bin - -ifneq ($(CONFIG_STITCH_ME_BIN),y) - -$(OBJ_ME_BIN): $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) - cp $< $@ - -endif - -add_intel_firmware: $(OBJ_ME_BIN) - -endif -ifeq ($(CONFIG_HAVE_GBE_BIN),y) -add_intel_firmware: $(call strip_quotes,$(CONFIG_GBE_BIN_PATH)) -endif -ifeq ($(CONFIG_HAVE_EC_BIN),y) -add_intel_firmware: $(call strip_quotes,$(CONFIG_EC_BIN_PATH)) -endif -add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(IFD_BIN_PATH) \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y) - printf " IFDTOOL validate IFD against FMAP\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) \ - -t $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) \ - -i ME:$(OBJ_ME_BIN) \ - -O $(obj)/coreboot.pre \ - $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_CHECK_ME),y) - util/me_cleaner/me_cleaner.py -c $(obj)/coreboot.pre > /dev/null -endif -ifeq ($(CONFIG_USE_ME_CLEANER),y) - printf " ME_CLEANER coreboot.pre\n" - util/me_cleaner/me_cleaner.py $(obj)/coreboot.pre \ - $(patsubst "%,%,$(patsubst %",%,$(CONFIG_ME_CLEANER_ARGS))) > \ - $(obj)/me_cleaner.log -endif -ifeq ($(CONFIG_HAVE_GBE_BIN),y) - printf " IFDTOOL gbe.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) \ - -i GbE:$(CONFIG_GBE_BIN_PATH) \ - -O $(obj)/coreboot.pre \ - $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_HAVE_EC_BIN),y) - printf " IFDTOOL ec.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) \ - -i EC:$(CONFIG_EC_BIN_PATH) \ - -O $(obj)/coreboot.pre \ - $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_HAVE_10GBE_0_BIN),y) - printf " IFDTOOL 10gbe0.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) \ - -i 10GbE_0:$(CONFIG_10GBE_0_BIN_PATH) \ - -O $(obj)/coreboot.pre \ - $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_HAVE_10GBE_1_BIN),y) - printf " IFDTOOL 10gbe1.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) \ - -i 10GbE_1:$(CONFIG_10GBE_1_BIN_PATH) \ - -O $(obj)/coreboot.pre \ - $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) $(IFDTOOL_LOCK_ME_MODE) \ - -O $(obj)/coreboot.pre \ - $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_UNLOCK_FLASH_REGIONS),y) - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) -u \ - -O $(obj)/coreboot.pre \ - $(obj)/coreboot.pre -endif - -ifeq ($(CONFIG_EM100),y) - printf " IFDTOOL Setting EM100 mode\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) --em100 \ - -O $(obj)/coreboot.pre \ - $(obj)/coreboot.pre -endif - -warn_intel_firmware: - printf "\n\t** WARNING **\n" - printf "coreboot has been built without an Intel Firmware Descriptor.\n" - printf "Never write a complete coreboot.rom without an IFD to your\n" - printf "board's flash chip! You can use flashrom's IFD or layout\n" - printf "parameters to flash only to the BIOS region.\n\n" - -PHONY+=warn_intel_firmware - -endif diff --git a/src/southbridge/intel/common/firmware/Makefile.mk b/src/southbridge/intel/common/firmware/Makefile.mk new file mode 100644 index 0000000000..1425d5a352 --- /dev/null +++ b/src/southbridge/intel/common/firmware/Makefile.mk @@ -0,0 +1,138 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) + +# Run intermediate steps when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS + +ifeq ($(CONFIG_HAVE_IFD_BIN),y) +$(call add_intermediate, add_intel_firmware) +else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) +show_notices:: warn_intel_firmware +endif + +IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) +ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),) +IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET) +endif + +ifeq ($(CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS),y) +IFDTOOL_LOCK_ME_MODE := -lr +else +IFDTOOL_LOCK_ME_MODE := -l +endif + +add_intel_firmware: $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) +ifeq ($(CONFIG_HAVE_ME_BIN),y) + +OBJ_ME_BIN := $(obj)/me.bin + +ifneq ($(CONFIG_STITCH_ME_BIN),y) + +$(OBJ_ME_BIN): $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) + cp $< $@ + +endif + +add_intel_firmware: $(OBJ_ME_BIN) + +endif +ifeq ($(CONFIG_HAVE_GBE_BIN),y) +add_intel_firmware: $(call strip_quotes,$(CONFIG_GBE_BIN_PATH)) +endif +ifeq ($(CONFIG_HAVE_EC_BIN),y) +add_intel_firmware: $(call strip_quotes,$(CONFIG_EC_BIN_PATH)) +endif +add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) + printf " DD Adding Intel Firmware Descriptor\n" + dd if=$(IFD_BIN_PATH) \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y) + printf " IFDTOOL validate IFD against FMAP\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -t $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_HAVE_ME_BIN),y) + printf " IFDTOOL me.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -i ME:$(OBJ_ME_BIN) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_CHECK_ME),y) + util/me_cleaner/me_cleaner.py -c $(obj)/coreboot.pre > /dev/null +endif +ifeq ($(CONFIG_USE_ME_CLEANER),y) + printf " ME_CLEANER coreboot.pre\n" + util/me_cleaner/me_cleaner.py $(obj)/coreboot.pre \ + $(patsubst "%,%,$(patsubst %",%,$(CONFIG_ME_CLEANER_ARGS))) > \ + $(obj)/me_cleaner.log +endif +ifeq ($(CONFIG_HAVE_GBE_BIN),y) + printf " IFDTOOL gbe.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -i GbE:$(CONFIG_GBE_BIN_PATH) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_HAVE_EC_BIN),y) + printf " IFDTOOL ec.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -i EC:$(CONFIG_EC_BIN_PATH) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_HAVE_10GBE_0_BIN),y) + printf " IFDTOOL 10gbe0.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -i 10GbE_0:$(CONFIG_10GBE_0_BIN_PATH) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_HAVE_10GBE_1_BIN),y) + printf " IFDTOOL 10gbe1.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -i 10GbE_1:$(CONFIG_10GBE_1_BIN_PATH) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) + printf " IFDTOOL Locking Management Engine\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) $(IFDTOOL_LOCK_ME_MODE) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_UNLOCK_FLASH_REGIONS),y) + printf " IFDTOOL Unlocking Management Engine\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) -u \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif + +ifeq ($(CONFIG_EM100),y) + printf " IFDTOOL Setting EM100 mode\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) --em100 \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif + +warn_intel_firmware: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without an Intel Firmware Descriptor.\n" + printf "Never write a complete coreboot.rom without an IFD to your\n" + printf "board's flash chip! You can use flashrom's IFD or layout\n" + printf "parameters to flash only to the BIOS region.\n\n" + +PHONY+=warn_intel_firmware + +endif diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc deleted file mode 100644 index 98dd33bda8..0000000000 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) - -bootblock-y += bootblock.c - -ramstage-y += i82371eb.c -ramstage-y += isa.c -ramstage-y += ide.c -ramstage-y += usb.c -ramstage-y += smbus.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c - -romstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c -romstage-y += early_pm.c -romstage-y += early_smbus.c - -endif diff --git a/src/southbridge/intel/i82371eb/Makefile.mk b/src/southbridge/intel/i82371eb/Makefile.mk new file mode 100644 index 0000000000..98dd33bda8 --- /dev/null +++ b/src/southbridge/intel/i82371eb/Makefile.mk @@ -0,0 +1,19 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) + +bootblock-y += bootblock.c + +ramstage-y += i82371eb.c +ramstage-y += isa.c +ramstage-y += ide.c +ramstage-y += usb.c +ramstage-y += smbus.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c + +romstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c +romstage-y += early_pm.c +romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc deleted file mode 100644 index 5db45379fe..0000000000 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y) - -bootblock-y += bootblock.c -bootblock-y += early_init.c - -romstage-y += early_init.c - -ramstage-y += i82801dx.c -ramstage-y += ac97.c -ramstage-y += fadt.c -ramstage-y += ide.c -ramstage-y += lpc.c -ramstage-y += usb.c -ramstage-y += usb2.c - -smm-y += smihandler.c - -endif diff --git a/src/southbridge/intel/i82801dx/Makefile.mk b/src/southbridge/intel/i82801dx/Makefile.mk new file mode 100644 index 0000000000..5db45379fe --- /dev/null +++ b/src/southbridge/intel/i82801dx/Makefile.mk @@ -0,0 +1,20 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y) + +bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += early_init.c + +ramstage-y += i82801dx.c +ramstage-y += ac97.c +ramstage-y += fadt.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += usb.c +ramstage-y += usb2.c + +smm-y += smihandler.c + +endif diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc deleted file mode 100644 index b6fd0c324a..0000000000 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) - -bootblock-y += early_init.c -bootblock-y += bootblock.c - -ramstage-y += i82801gx.c -ramstage-y += fadt.c -ramstage-y += ac97.c -ramstage-y += azalia.c -ramstage-y += ide.c -ramstage-y += lpc.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += sata.c -ramstage-y += smbus.c -ramstage-y += usb.c -ramstage-y += usb_ehci.c - -smm-y += smihandler.c - -romstage-y += early_init.c -romstage-y += early_cir.c - -CPPFLAGS_common += -I$(src)/southbridge/intel/i82801gx/include - -endif diff --git a/src/southbridge/intel/i82801gx/Makefile.mk b/src/southbridge/intel/i82801gx/Makefile.mk new file mode 100644 index 0000000000..b6fd0c324a --- /dev/null +++ b/src/southbridge/intel/i82801gx/Makefile.mk @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) + +bootblock-y += early_init.c +bootblock-y += bootblock.c + +ramstage-y += i82801gx.c +ramstage-y += fadt.c +ramstage-y += ac97.c +ramstage-y += azalia.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += smbus.c +ramstage-y += usb.c +ramstage-y += usb_ehci.c + +smm-y += smihandler.c + +romstage-y += early_init.c +romstage-y += early_cir.c + +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801gx/include + +endif diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc deleted file mode 100644 index 8db30ad64a..0000000000 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ /dev/null @@ -1,27 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y) - -bootblock-y += bootblock.c -bootblock-y += early_init.c - -romstage-y += dmi_setup.c -romstage-y += early_init.c - -ramstage-y += azalia.c -ramstage-y += fadt.c -ramstage-y += i82801ix.c -ramstage-y += lpc.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += sata.c -ramstage-y += smbus.c -ramstage-y += thermal.c -ramstage-y += usb_ehci.c -ramstage-y += ../common/pciehp.c - -smm-y += smihandler.c - -CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include - -endif diff --git a/src/southbridge/intel/i82801ix/Makefile.mk b/src/southbridge/intel/i82801ix/Makefile.mk new file mode 100644 index 0000000000..8db30ad64a --- /dev/null +++ b/src/southbridge/intel/i82801ix/Makefile.mk @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y) + +bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += dmi_setup.c +romstage-y += early_init.c + +ramstage-y += azalia.c +ramstage-y += fadt.c +ramstage-y += i82801ix.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += usb_ehci.c +ramstage-y += ../common/pciehp.c + +smm-y += smihandler.c + +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include + +endif diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc deleted file mode 100644 index f1388ce42d..0000000000 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) - -bootblock-y += bootblock.c -bootblock-y += early_init.c - -romstage-y += early_init.c - -ramstage-y += azalia.c -ramstage-y += fadt.c -ramstage-y += i82801jx.c -ramstage-y += lpc.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += sata.c -ramstage-y += smbus.c -ramstage-y += thermal.c -ramstage-y += usb_ehci.c -ramstage-y += ../common/pciehp.c - -smm-y += smihandler.c - -endif diff --git a/src/southbridge/intel/i82801jx/Makefile.mk b/src/southbridge/intel/i82801jx/Makefile.mk new file mode 100644 index 0000000000..f1388ce42d --- /dev/null +++ b/src/southbridge/intel/i82801jx/Makefile.mk @@ -0,0 +1,24 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) + +bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += early_init.c + +ramstage-y += azalia.c +ramstage-y += fadt.c +ramstage-y += i82801jx.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += usb_ehci.c +ramstage-y += ../common/pciehp.c + +smm-y += smihandler.c + +endif diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc deleted file mode 100644 index 83ebca5af2..0000000000 --- a/src/southbridge/intel/i82870/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y) - -ramstage-y += ioapic.c -ramstage-y += pcibridge.c - -endif diff --git a/src/southbridge/intel/i82870/Makefile.mk b/src/southbridge/intel/i82870/Makefile.mk new file mode 100644 index 0000000000..83ebca5af2 --- /dev/null +++ b/src/southbridge/intel/i82870/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y) + +ramstage-y += ioapic.c +ramstage-y += pcibridge.c + +endif diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc deleted file mode 100644 index 99968f8bcc..0000000000 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ /dev/null @@ -1,35 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) - -bootblock-y += bootblock.c - -ramstage-y += pch.c -ramstage-y += azalia.c -ramstage-y += fadt.c -ramstage-y += lpc.c -ramstage-y += ../bd82x6x/pci.c -ramstage-y += sata.c -ramstage-y += usb_ehci.c -ramstage-y += me.c -ramstage-y += ../bd82x6x/me_common.c -ramstage-y += smbus.c -ramstage-y += thermal.c -ramstage-y += ../common/pciehp.c - -ramstage-y += ../bd82x6x/me_status.c - -ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c - -smm-y += smihandler.c - -romstage-y += early_pch.c -romstage-y +=../bd82x6x/early_me.c -romstage-y +=../bd82x6x/me_status.c -romstage-y += early_thermal.c -romstage-y += ../bd82x6x/early_rcba.c -romstage-y += early_cir.c -romstage-y += early_usb.c -romstage-y += setup_heci_uma.c - -endif diff --git a/src/southbridge/intel/ibexpeak/Makefile.mk b/src/southbridge/intel/ibexpeak/Makefile.mk new file mode 100644 index 0000000000..99968f8bcc --- /dev/null +++ b/src/southbridge/intel/ibexpeak/Makefile.mk @@ -0,0 +1,35 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) + +bootblock-y += bootblock.c + +ramstage-y += pch.c +ramstage-y += azalia.c +ramstage-y += fadt.c +ramstage-y += lpc.c +ramstage-y += ../bd82x6x/pci.c +ramstage-y += sata.c +ramstage-y += usb_ehci.c +ramstage-y += me.c +ramstage-y += ../bd82x6x/me_common.c +ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += ../common/pciehp.c + +ramstage-y += ../bd82x6x/me_status.c + +ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c + +smm-y += smihandler.c + +romstage-y += early_pch.c +romstage-y +=../bd82x6x/early_me.c +romstage-y +=../bd82x6x/me_status.c +romstage-y += early_thermal.c +romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c +romstage-y += early_usb.c +romstage-y += setup_heci_uma.c + +endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc deleted file mode 100644 index 5088d8bb2d..0000000000 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ /dev/null @@ -1,60 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) - -bootblock-y += bootblock.c - -ramstage-y += pch.c -ramstage-y += iobp.c -ramstage-y += azalia.c -ramstage-y += fadt.c -ramstage-y += lpc.c -ramstage-y += pcie.c -ramstage-y += sata.c -ramstage-y += usb_ehci.c -ramstage-y += usb_xhci.c -ramstage-y += me.c -ramstage-y += smbus.c -ramstage-y += hda_verb.c -ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c - -ifneq ($(CONFIG_VARIANT_DIR),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/hda_verb.c -endif - -ramstage-y += me_status.c -ramstage-y += acpi.c - -ramstage-$(CONFIG_ELOG) += elog.c - -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c -smm-y += smihandler.c pch.c -smm-y += pmutil.c usb_ehci.c usb_xhci.c - -bootblock-y += early_pch.c -romstage-y += early_usb.c early_me.c me_status.c early_pch.c -romstage-y += pmutil.c -romstage-y += iobp.c - -romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c -subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio - -romstage-$(CONFIG_USE_BROADWELL_MRC) += early_pch_native.c early_usb_native.c iobp.c thermal.c -subdirs-$(CONFIG_USE_BROADWELL_MRC) += hsio - -ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) -romstage-y += lp_gpio.c -ramstage-y += lp_gpio.c -smm-y += lp_gpio.c -verstage-y += lp_gpio.c -bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += uart_init.c -bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += iobp.c -all-$(CONFIG_SERIALIO_UART_CONSOLE) += uart.c -smm-$(CONFIG_SERIALIO_UART_CONSOLE) += uart.c -endif - -verstage-y += pmutil.c - -CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include - -endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.mk b/src/southbridge/intel/lynxpoint/Makefile.mk new file mode 100644 index 0000000000..5088d8bb2d --- /dev/null +++ b/src/southbridge/intel/lynxpoint/Makefile.mk @@ -0,0 +1,60 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) + +bootblock-y += bootblock.c + +ramstage-y += pch.c +ramstage-y += iobp.c +ramstage-y += azalia.c +ramstage-y += fadt.c +ramstage-y += lpc.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += usb_ehci.c +ramstage-y += usb_xhci.c +ramstage-y += me.c +ramstage-y += smbus.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c + +ifneq ($(CONFIG_VARIANT_DIR),) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/hda_verb.c +endif + +ramstage-y += me_status.c +ramstage-y += acpi.c + +ramstage-$(CONFIG_ELOG) += elog.c + +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c +smm-y += smihandler.c pch.c +smm-y += pmutil.c usb_ehci.c usb_xhci.c + +bootblock-y += early_pch.c +romstage-y += early_usb.c early_me.c me_status.c early_pch.c +romstage-y += pmutil.c +romstage-y += iobp.c + +romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c +subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio + +romstage-$(CONFIG_USE_BROADWELL_MRC) += early_pch_native.c early_usb_native.c iobp.c thermal.c +subdirs-$(CONFIG_USE_BROADWELL_MRC) += hsio + +ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +romstage-y += lp_gpio.c +ramstage-y += lp_gpio.c +smm-y += lp_gpio.c +verstage-y += lp_gpio.c +bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += uart_init.c +bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += iobp.c +all-$(CONFIG_SERIALIO_UART_CONSOLE) += uart.c +smm-$(CONFIG_SERIALIO_UART_CONSOLE) += uart.c +endif + +verstage-y += pmutil.c + +CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include + +endif diff --git a/src/southbridge/intel/lynxpoint/hsio/Makefile.inc b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc deleted file mode 100644 index 6b74997511..0000000000 --- a/src/southbridge/intel/lynxpoint/hsio/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -romstage-y += common.c -ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) -romstage-y += lpt_lp_bx.c -else -romstage-y += lpt_h_cx.c -endif diff --git a/src/southbridge/intel/lynxpoint/hsio/Makefile.mk b/src/southbridge/intel/lynxpoint/hsio/Makefile.mk new file mode 100644 index 0000000000..6b74997511 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/hsio/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +romstage-y += common.c +ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +romstage-y += lpt_lp_bx.c +else +romstage-y += lpt_h_cx.c +endif diff --git a/src/southbridge/ricoh/rl5c476/Makefile.inc b/src/southbridge/ricoh/rl5c476/Makefile.inc deleted file mode 100644 index 24e84d24e7..0000000000 --- a/src/southbridge/ricoh/rl5c476/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y) - -ramstage-y += rl5c476.c - -endif diff --git a/src/southbridge/ricoh/rl5c476/Makefile.mk b/src/southbridge/ricoh/rl5c476/Makefile.mk new file mode 100644 index 0000000000..24e84d24e7 --- /dev/null +++ b/src/southbridge/ricoh/rl5c476/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y) + +ramstage-y += rl5c476.c + +endif diff --git a/src/southbridge/ti/pci1x2x/Makefile.inc b/src/southbridge/ti/pci1x2x/Makefile.inc deleted file mode 100644 index 05e57add48..0000000000 --- a/src/southbridge/ti/pci1x2x/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y) - -ramstage-y += pci1x2x.c - -endif diff --git a/src/southbridge/ti/pci1x2x/Makefile.mk b/src/southbridge/ti/pci1x2x/Makefile.mk new file mode 100644 index 0000000000..05e57add48 --- /dev/null +++ b/src/southbridge/ti/pci1x2x/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y) + +ramstage-y += pci1x2x.c + +endif diff --git a/src/southbridge/ti/pci7420/Makefile.inc b/src/southbridge/ti/pci7420/Makefile.inc deleted file mode 100644 index 07794cfe7d..0000000000 --- a/src/southbridge/ti/pci7420/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI7420),y) - -ramstage-y += cardbus.c -ramstage-y += firewire.c - -endif diff --git a/src/southbridge/ti/pci7420/Makefile.mk b/src/southbridge/ti/pci7420/Makefile.mk new file mode 100644 index 0000000000..07794cfe7d --- /dev/null +++ b/src/southbridge/ti/pci7420/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI7420),y) + +ramstage-y += cardbus.c +ramstage-y += firewire.c + +endif diff --git a/src/southbridge/ti/pcixx12/Makefile.inc b/src/southbridge/ti/pcixx12/Makefile.inc deleted file mode 100644 index 337a42c133..0000000000 --- a/src/southbridge/ti/pcixx12/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCIXX12),y) - -ramstage-y += pcixx12.c - -endif diff --git a/src/southbridge/ti/pcixx12/Makefile.mk b/src/southbridge/ti/pcixx12/Makefile.mk new file mode 100644 index 0000000000..337a42c133 --- /dev/null +++ b/src/southbridge/ti/pcixx12/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCIXX12),y) + +ramstage-y += pcixx12.c + +endif -- cgit v1.2.3