From 8a5ee9ce04cb88a57cf0a0d8a405c9865c99c01a Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 10 Jan 2013 11:44:58 -0800 Subject: armv7: replace magic constant for romstage location This replaces 0x02023400 with an SoC-specific Kconfig variable. Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551 Signed-off-by: David Hendricks Reviewed-on: http://review.coreboot.org/2130 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/armv7/romstage.ld | 3 +-- src/mainboard/google/snow/Kconfig | 4 ++++ 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 4429af47dc..b63a78e05e 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -39,8 +39,7 @@ ENTRY(_start) SECTIONS { - /* FIXME: replace this with CPU-specific Kconfig variable */ - . = 0x02023400; /* Exynos5 */ + . = CONFIG_ROMSTAGE_BASE; .romtext . : { _rom = .; diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 4a7fced3c0..21cdfa5fd2 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -63,6 +63,10 @@ config SPL_TEXT_BASE help Location of SPL. Default location is within iRAM region. +config ROMSTAGE_BASE + hex + default SPL_TEXT_BASE + # FIXME: increased "SPL" size to get around build issues #config SPL_MAX_SIZE # hex "SPL executable max size" -- cgit v1.2.3