From 88d8e2b74eb9b2b3186ccb519efd1dbd92a090cb Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 3 Dec 2020 18:17:57 +0100 Subject: soc/amd/picassso/acpi: increase MMIO region size of GPIO controller The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256 bytes each, so increase the reserved size to match the hardware. Also replace the base GPIO address with the corresponding define. Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/acpi/sb_fch.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 6cbfc5f664..c4dffed8af 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -34,7 +34,7 @@ Device (GPIO) ActiveLow, Exclusive, , , IRQR) { 0 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) } CreateDWordField (Local0, IRQR._INT, IRQN) If (PMOD) { @@ -44,7 +44,7 @@ Device (GPIO) } If (IRQN == 0x1f) { Return (ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) }) } Else { Return (Local0) -- cgit v1.2.3