From 8823ba167318e87f74717d0c32e29b58a1ed3eca Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Mon, 5 Dec 2022 08:48:50 +0100
Subject: treewide: Include <device/mmio.h> instead of <arch/mmio.h>

<device/mmio.h>` chain-include `<arch/mmio.h>:
https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes

Also sort includes while on it.

Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/device/xhci.c                                      | 2 +-
 src/drivers/emulation/qemu/bochs.c                     | 8 ++++----
 src/drivers/intel/ptt/ptt.c                            | 6 +++---
 src/drivers/siemens/nc_fpga/nc_fpga_early.c            | 2 +-
 src/include/cpu/x86/lapic.h                            | 2 +-
 src/mainboard/google/dedede/fw_config.c                | 2 +-
 src/mainboard/google/dedede/variants/bugzzy/ramstage.c | 6 +++---
 src/mainboard/protectli/vault_bsw/mainboard.c          | 2 +-
 src/mainboard/scaleway/tagada/hsio.c                   | 6 +++---
 src/mainboard/siemens/mc_ehl/romstage_fsp_params.c     | 2 +-
 src/northbridge/intel/x4x/bootblock.c                  | 2 +-
 src/security/intel/txt/common.c                        | 4 ++--
 src/security/intel/txt/logging.c                       | 2 +-
 src/security/intel/txt/ramstage.c                      | 2 +-
 src/security/intel/txt/romstage.c                      | 2 +-
 src/soc/amd/common/block/acpi/ivrs.c                   | 2 +-
 src/soc/amd/common/block/psp/psb.c                     | 5 +++--
 src/soc/amd/common/block/psp/psp_efs.c                 | 2 +-
 src/soc/amd/common/block/spi/fch_spi.c                 | 2 +-
 src/soc/amd/picasso/agesa_acpi.c                       | 2 +-
 src/soc/intel/alderlake/bootblock/update_descriptor.c  | 2 +-
 src/southbridge/intel/lynxpoint/uart_init.c            | 2 +-
 22 files changed, 34 insertions(+), 33 deletions(-)

(limited to 'src')

diff --git a/src/device/xhci.c b/src/device/xhci.c
index 4523b56adc..f7c5958a6c 100644
--- a/src/device/xhci.c
+++ b/src/device/xhci.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <arch/mmio.h>
 #include <console/console.h>
+#include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/xhci.h>
 #include <string.h>
diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c
index d3b9007abe..4634021b67 100644
--- a/src/drivers/emulation/qemu/bochs.c
+++ b/src/drivers/emulation/qemu/bochs.c
@@ -1,16 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
 #include <arch/io.h>
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/pci.h>
-#include <device/pci_ops.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <framebuffer_info.h>
 #include <pc80/vga.h>
 #include <pc80/vga_io.h>
-#include <framebuffer_info.h>
+#include <stdint.h>
 
 /* VGA init. We use the Bochs VESA VBE extensions  */
 #define VBE_DISPI_IOPORT_INDEX          0x01CE
diff --git a/src/drivers/intel/ptt/ptt.c b/src/drivers/intel/ptt/ptt.c
index 5b0918bada..76b8ed6c91 100644
--- a/src/drivers/intel/ptt/ptt.c
+++ b/src/drivers/intel/ptt/ptt.c
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
-#include <soc/pci_devs.h>
-#include <device/pci_ops.h>
 #include <console/console.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
 #include <security/intel/txt/txt_register.h>
+#include <soc/pci_devs.h>
 #include <stdint.h>
 
 #include "ptt.h"
diff --git a/src/drivers/siemens/nc_fpga/nc_fpga_early.c b/src/drivers/siemens/nc_fpga/nc_fpga_early.c
index 44ed97a49f..8cdc1f9106 100644
--- a/src/drivers/siemens/nc_fpga/nc_fpga_early.c
+++ b/src/drivers/siemens/nc_fpga/nc_fpga_early.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
+#include <device/mmio.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index cfb9c9098b..f7fecf1342 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -3,10 +3,10 @@
 #ifndef CPU_X86_LAPIC_H
 #define CPU_X86_LAPIC_H
 
-#include <arch/mmio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
+#include <device/mmio.h>
 #include <halt.h>
 #include <stdint.h>
 
diff --git a/src/mainboard/google/dedede/fw_config.c b/src/mainboard/google/dedede/fw_config.c
index 7e5d8fa2e2..d176283c2a 100644
--- a/src/mainboard/google/dedede/fw_config.c
+++ b/src/mainboard/google/dedede/fw_config.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <bootstate.h>
+#include <device/mmio.h>
 #include <fw_config.h>
 #include <gpio.h>
 #include <intelblocks/gpio.h>
diff --git a/src/mainboard/google/dedede/variants/bugzzy/ramstage.c b/src/mainboard/google/dedede/variants/bugzzy/ramstage.c
index 7844b6e360..8fb448dd45 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/ramstage.c
+++ b/src/mainboard/google/dedede/variants/bugzzy/ramstage.c
@@ -1,13 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <bootmode.h>
 #include <bootstate.h>
-#include <arch/mmio.h>
 #include <delay.h>
-#include <bootmode.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/pci.h>
-#include <soc/pci_devs.h>
 #include <drivers/intel/gma/i915_reg.h>
+#include <soc/pci_devs.h>
 
 static void panel_power_on(uintptr_t igd_bar)
 {
diff --git a/src/mainboard/protectli/vault_bsw/mainboard.c b/src/mainboard/protectli/vault_bsw/mainboard.c
index 3c9c45c476..ec4f81635e 100644
--- a/src/mainboard/protectli/vault_bsw/mainboard.c
+++ b/src/mainboard/protectli/vault_bsw/mainboard.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <arch/mmio.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <soc/iomap.h>
 
 #define BIOS_CONTROL_REG	0xFC
diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c
index d305427f02..d6fb676ba0 100644
--- a/src/mainboard/scaleway/tagada/hsio.c
+++ b/src/mainboard/scaleway/tagada/hsio.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <console/console.h>
-#include <hsio.h>
+#include <device/mmio.h>
+#include <fast_spi_def.h>
 #include <gpio_defs.h>
+#include <hsio.h>
 #include <soc/fiamux.h>
 #include <string.h>
-#include <fast_spi_def.h>
 
 #ifdef __RAMSTAGE__
 static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATION *config)
diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
index 7befa4a9db..506bcc6824 100644
--- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <baseboard/variants.h>
 #include <console/console.h>
 #include <device/dram/common.h>
+#include <device/mmio.h>
 #include <hwilib.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 71a0609e55..123385961f 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/bootblock.h>
-#include <arch/mmio.h>
 #include <assert.h>
+#include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <types.h>
 
diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c
index b88062d42b..b78394add2 100644
--- a/src/security/intel/txt/common.c
+++ b/src/security/intel/txt/common.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
-#include <console/console.h>
 #include <cbfs.h>
+#include <console/console.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <device/mmio.h>
 #include <lib.h>
 #include <smp/node.h>
 #include <string.h>
diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c
index e3fcb5e274..6485b867e2 100644
--- a/src/security/intel/txt/logging.c
+++ b/src/security/intel/txt/logging.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
+#include <device/mmio.h>
 #include <types.h>
 
 #include "txt.h"
diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c
index 744b05e410..8a266a4230 100644
--- a/src/security/intel/txt/ramstage.c
+++ b/src/security/intel/txt/ramstage.c
@@ -1,13 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <arch/mmio.h>
 #include <bootmem.h>
 #include <bootstate.h>
 #include <cbfs.h>
 #include <console/console.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/smm.h>
+#include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <security/intel/cbnt/cbnt.h>
 #include <types.h>
diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c
index e045c9d6fb..e1329dd957 100644
--- a/src/security/intel/txt/romstage.c
+++ b/src/security/intel/txt/romstage.c
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/cpu.h>
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/msr.h>
+#include <device/mmio.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <timer.h>
 #include <types.h>
diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index 1b4257a2fc..0c5853a2c0 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -6,11 +6,11 @@
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/ioapic.h>
 #include <arch/ioapic.h>
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <cpu/amd/cpuid.h>
 #include <cpu/amd/msr.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <soc/acpi.h>
diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c
index 58b957d4d7..be5d43b40d 100644
--- a/src/soc/amd/common/block/psp/psb.c
+++ b/src/soc/amd/common/block/psp/psb.c
@@ -1,12 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
-#include <bootstate.h>
 #include <amdblocks/reset.h>
 #include <amdblocks/smn.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <cpu/amd/msr.h>
+#include <device/mmio.h>
 #include <types.h>
+
 #include "psp_def.h"
 
 #define PSB_STATUS_OFFSET	0x10994
diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c
index eacd5f637c..709273e8d8 100644
--- a/src/soc/amd/common/block/psp/psp_efs.c
+++ b/src/soc/amd/common/block/psp/psp_efs.c
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/psp_efs.h>
-#include <arch/mmio.h>
 #include <assert.h>
 #include <boot_device.h>
 #include <commonlib/region.h>
+#include <device/mmio.h>
 #include <types.h>
 
 static struct embedded_firmware *efs;
diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
index 4a8482e97e..d9708b1eb0 100644
--- a/src/soc/amd/common/block/spi/fch_spi.c
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -4,8 +4,8 @@
 #include <amdblocks/lpc.h>
 #include <amdblocks/psp_efs.h>
 #include <amdblocks/spi.h>
-#include <arch/mmio.h>
 #include <console/console.h>
+#include <device/mmio.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <stdint.h>
diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c
index 839d7c0652..1e6a6d4765 100644
--- a/src/soc/amd/picasso/agesa_acpi.c
+++ b/src/soc/amd/picasso/agesa_acpi.c
@@ -7,11 +7,11 @@
 #include <amdblocks/cpu.h>
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/ioapic.h>
-#include <arch/mmio.h>
 #include <cpu/amd/cpuid.h>
 #include <cpu/amd/msr.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <FspGuids.h>
diff --git a/src/soc/intel/alderlake/bootblock/update_descriptor.c b/src/soc/intel/alderlake/bootblock/update_descriptor.c
index 9c8ce9c732..11e7ccddfe 100644
--- a/src/soc/intel/alderlake/bootblock/update_descriptor.c
+++ b/src/soc/intel/alderlake/bootblock/update_descriptor.c
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <arch/mmio.h>
 #include <cf9_reset.h>
 #include <commonlib/region.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/cpu_ids.h>
+#include <device/mmio.h>
 #include <fmap.h>
 #include <intelblocks/pmclib.h>
 #include <soc/bootblock.h>
diff --git a/src/southbridge/intel/lynxpoint/uart_init.c b/src/southbridge/intel/lynxpoint/uart_init.c
index 66b9e01981..5048e5d545 100644
--- a/src/southbridge/intel/lynxpoint/uart_init.c
+++ b/src/southbridge/intel/lynxpoint/uart_init.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/io.h>
-#include <arch/mmio.h>
 #include <assert.h>
 #include <console/uart.h>
+#include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
-- 
cgit v1.2.3