From 87b5ff0124f86e48c38856ee7dbaa5436f7af2fd Mon Sep 17 00:00:00 2001 From: Patrick Rudolph <siro@das-labor.org> Date: Sun, 28 May 2017 13:57:04 +0200 Subject: sb/intel/bd82x6x/early_usb: Use register name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use register name instead of magic value. Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> --- src/southbridge/intel/bd82x6x/early_usb.c | 6 ++++-- src/southbridge/intel/bd82x6x/pch.h | 4 ++++ 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 81d3b6b505..339a835674 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -37,7 +37,9 @@ early_usb_init (const struct southbridge_usb_port *portmap) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ /* Unlock registers. */ - outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, + DEFAULT_PMBASE | UPRWC); + for (i = 0; i < 14; i++) write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i), currents[portmap[i].current]); @@ -69,5 +71,5 @@ early_usb_init (const struct southbridge_usb_port *portmap) pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); /* Relock registers. */ - outw (0x0000, DEFAULT_PMBASE | 0x003c); + outw(0, DEFAULT_PMBASE | UPRWC); } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index f8131da062..1e05c9c035 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -113,6 +113,10 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif +/* PM I/O Space */ +#define UPRWC 0x3c +#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ + /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b -- cgit v1.2.3