From 870fe79e64d46db10e5a58ef88a79e97f0dfec4d Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 7 Nov 2017 13:26:52 -0700 Subject: amd/stoneyridge: Add more ACPI register definitions Change-Id: I62a840499deed895cf474f1bfce1f399c970e589 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/22411 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src') diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index cdcebb1606..112b610a18 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -55,6 +55,18 @@ #define PM_SERIRQ_ENABLE BIT(7) #define PM_EVT_BLK 0x60 +#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ +#define PCIEXPWAK_STS BIT(14) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TIMER_STS BIT(0) +#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TIMER_STS BIT(0) #define PM1_CNT_BLK 0x62 #define PM_TMR_BLK 0x64 #define PM_CPU_CTRL 0x66 -- cgit v1.2.3