From 85654a66504f2c87f129d3c414995be4b6cdc09f Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 4 Aug 2015 14:04:47 -0500 Subject: skylake: set DISB in GEN_PMCON_A register properly DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM training is complete. However, as a 8-bit write was being performed the bit was never being set. BUG=chrome-os-partner:43516 BRANCH=None TEST=Built and booted to kernel. Rebooted. Noted full memory training was not being peformed. Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/290337 Original-Reviewed-by: Duncan Laurie Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11183 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/pmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index b62a28886b..a97f7517fa 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -47,7 +47,7 @@ static const struct reg_script pch_pmc_misc_init_script[] = { /* Enable SCI and clear SLP requests. */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), /* Indicate DRAM init done for MRC */ - REG_PCI_OR8(GEN_PMCON_A, DISB), + REG_PCI_OR32(GEN_PMCON_A, DISB), REG_SCRIPT_END }; -- cgit v1.2.3