From 8488853fab0417b222ae04924574bd6f2221ca0e Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 5 Mar 2020 00:54:02 -0800 Subject: soc/intel/tigerlake: Enable CNVi Mode Add configs to enable CNVi mode and CNViBtCore. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39317 Reviewed-by: Nick Vaccaro Reviewed-by: caveh jalali Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 4 ++++ src/soc/intel/tigerlake/fsp_params_tgl.c | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'src') diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e57abe857b..a6bcf0847f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -208,6 +208,10 @@ struct soc_intel_tigerlake_config { /* Enable Pch iSCLK */ uint8_t pch_isclk; + /* CNVi */ + uint8_t CnviMode; + uint8_t CnviBtCore; + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { FORCE_DISABLE, diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 9e22b58e7c..0dae0fed47 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -149,6 +149,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->PchLanEnable = dev->enabled; + /* CNVi */ + params->CnviMode = config->CnviMode; + params->CnviBtCore = config->CnviBtCore; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; -- cgit v1.2.3