From 845c861244f1e8b262c3944bb7330f28bb73ea52 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 14 Nov 2024 13:36:57 -0700 Subject: mb/google/brox: Reset XHCI controller while preparing for S5 This patch calls `xhci_host_reset()` function to perform XHCI controller reset. This is proactively pulled in to avoid any potential timeouts when PMC sends an IPC command to disconnect the active USB ports. BUG=b:364158487 TEST=Build Brox BIOS image and boot to OS. Perform warm reset, cold reset and suspend/resume cycle. Change-Id: I33fd3aa13e81c7b1ae1ebf6674cc8ac1437ecc03 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/85141 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: --- src/mainboard/google/brox/smihandler.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/brox/smihandler.c b/src/mainboard/google/brox/smihandler.c index 21b441f8d9..d583d4f00c 100644 --- a/src/mainboard/google/brox/smihandler.c +++ b/src/mainboard/google/brox/smihandler.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include #include #include #include +#include #include void __weak variant_smi_sleep(u8 slp_typ) {} @@ -14,6 +16,12 @@ void mainboard_smi_sleep(u8 slp_typ) { variant_smi_sleep(slp_typ); chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); + /* + * Workaround: Reset the XHCI controller prior to S5 to avoid + * PMC timeout error during poweron from S5. + */ + if (slp_typ == ACPI_S5) + xhci_host_reset(); } int mainboard_smi_apmc(u8 apmc) -- cgit v1.2.3