From 8417485f95b07aa76d81d7006fa5097d018d6df2 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 28 Jun 2019 16:12:47 +0200 Subject: soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP We got rid of the dangerous reconfiguration of arbitrary pads in coreboot, but FSP still overrode that. Make sure that it doesn't enable a UART for debug output when it isn't configured in core- boot. This, again, shows how dangerous it is to leave any FSP UPD at its binary default. Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a58a97c060..2367045bdb 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -285,6 +285,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set Debug serial port */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; +#if !CONFIG(SOC_INTEL_COMETLAKE) + params->SerialIoEnableDebugUartAfterPost = CONFIG_INTEL_LPSS_UART_FOR_CONSOLE; +#endif /* Enable CNVi Wifi if enabled in device tree */ dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); -- cgit v1.2.3