From 8256ca0e14e57b17b27a81b16f220c94d728e117 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 21 Oct 2019 18:47:46 +0200 Subject: soc/intel/braswell: Update microcode before FSP The google FSP Braswell version has broken microcode update code and FSP checks at some point if the installed microcode version is non zero, so coreboot has to update it before calling FSP-T. This is fixed with newer FSP releases by Intel, but doing updates in coreboot won't hurt. Tested with both Intel FSP and google FSP. Change-Id: I3e81329854e823dc66fec191adbed617bb37d649 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36198 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/Makefile.inc | 1 + src/drivers/intel/fsp1_1/cache_as_ram.S | 41 +++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) (limited to 'src') diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 85c4e0e608..014311897f 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -19,6 +19,7 @@ verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c +bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S romstage-y += car.c romstage-y += fsp_util.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index ffafe9b4f3..f4638d9c18 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include +#include #include /* @@ -43,6 +45,45 @@ bootblock_pre_c_entry: cache_as_ram: post_code(0x20) + /* Cache the rom and update the microcode */ +cache_rom: + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable cache */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* The Google FSP release for Braswell has broken microcode update + code and FSP needs the installed microcode revision to be non zero. + It is better to have coreboot do it instead of relying on a fragile + blob. */ +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: + /* * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. -- cgit v1.2.3