From 800b0173c98101ee6ad2c7eaf1951a435c819fd9 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 29 Apr 2016 12:10:28 -0500 Subject: arch/x86/asembly_entry: reorder conditional stage entry macros The path that just clears CAR_GLOBAL variables and jumps to the stage entry point needs another condition for separate verstage just after bootblock. However, the current conditional is a negative conditional so swap the logic around to make it easier to extend. Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/14547 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Andrey Petrov Reviewed-by: Leroy P Leahy --- src/arch/x86/assembly_entry.S | 44 ++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 11babe1273..ec3888fa43 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -14,28 +14,8 @@ * GNU General Public License for more details. */ -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) - -/* This file assembles the start of the romstage program by the order of the - * includes. Thus, it's extremely important that one pays very careful - * attention to the order of the includes. */ - -#include -#include -#include -#if IS_ENABLED(CONFIG_SSE) -#include -#endif +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) -/* - * The assembly.inc is generated based on the requirements of the mainboard. - * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be - * processed by ROMCC and added. In non-ROMCC boards the chipsets' - * cache-as-ram setup files would be here. - */ -#include - -#else /* * This path is for stages that post bootblock when employing * CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc @@ -65,4 +45,26 @@ _start: car_stage_entry: 1: jmp 1b + +#else + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include +#include +#include +#if IS_ENABLED(CONFIG_SSE) +#include +#endif + +/* + * The assembly.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include + #endif -- cgit v1.2.3