From 7ece43aeb5c5c10a9dcea8d05418b457e5d2f158 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 17 Sep 2024 15:38:42 +0530 Subject: soc/intel: Move CSE update ELOG to cse_lite.c The ELOG for CSE updates was being added in fsp_params.c, but the actual update happens in cse_lite.c. This commit moves the ELOG to cse_lite.c to more accurately reflect where the event is happening. This also removes the need for a sol_type variable in meteorlake/romstage/fsp_params.c. It also helps to avoid redundant ELOG event entry while performing CSE update (due to CSE RO to RW switch dependency). BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo) TEST=Able to see only one instance of ELOG while performimg CSE sync. w/o this patch: elogtool list 0 | Log area cleared | 4088 1 | Kernel Event | Clean Shutdown 2 | Early Sign of Life | MRC Early SOL Screen Shown 3 | Early Sign of Life | CSE Sync Early SOL Screen Shown 4 | System boot | 29 5 | Memory Cache Update | Normal | Success 6 | Early Sign of Life | CSE Sync Early SOL Screen Shown w/ this patch: elogtool list 0 | Log area cleared | 4088 1 | Early Sign of Life | MRC Early SOL Screen Shown 2 | Memory Cache Update | Normal | Success 3 | System boot | 30 4 | Memory Cache Update | Normal | Success 5 | Early Sign of Life | CSE Sync Early SOL Screen Shown Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Jakub Czapiga Reviewed-by: Jayvik Desai --- src/soc/intel/alderlake/romstage/fsp_params.c | 2 -- src/soc/intel/common/block/cse/cse_lite.c | 1 + src/soc/intel/meteorlake/romstage/fsp_params.c | 8 ++------ 3 files changed, 3 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index d4608eee26..969e15f51a 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -445,8 +445,6 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, name = "CSE update"; esol_required = true; } - - elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); } if (esol_required) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 8f59724023..a7389f8baa 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -835,6 +835,7 @@ static enum cb_err cse_write_rw_region(const struct region_device *target_rdev, return CB_ERR; printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); return CB_SUCCESS; } diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 84e665d929..917503ed98 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -447,19 +447,16 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, void *vbt; size_t vbt_size; uint32_t vga_init_control = 0; - uint8_t sol_type; /* Memory training. */ if (!arch_upd->NvsBufferPtr) { vga_init_control = VGA_INIT_CONTROL_ENABLE | VGA_INIT_CONTROL_TEAR_DOWN; - sol_type = ELOG_FW_EARLY_SOL_MRC; + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); } - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) vga_init_control = VGA_INIT_CONTROL_ENABLE; - sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC; - } if (!vga_init_control) return; @@ -478,7 +475,6 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, } printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); - elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type); m_cfg->VgaInitControl = vga_init_control; m_cfg->VbtPtr = (efi_uintn_t)vbt; -- cgit v1.2.3