From 7eaac6cdc1056bb99b92fc8618ae26af8d5ec111 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Fri, 24 Jul 2020 21:57:10 -0700 Subject: soc/intel/tigerlake: Invoke PCIe root port swapping PCIe bus:function specifiers need to be coalesced the same way functions are coalesced during bus enumeration. Invoke PCIe root port devicetree update to swap the enabled root port devices with the disabled devices. At this point, the TGL pci_devs.h only describes the PCH-LP, so only the PCH-LP root ports are listed in this patch. We'll need to add additional PCIe root ports when PCH-H support is added. BUG=b:162106164 TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is swapped with the PCIe device 1c.0 corresponding to Root port 1. Change-Id: I9230de8b1818f3f2115dab923841fd0e7778be62 Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/43850 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/chip.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src') diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index d08355e019..d3c3c62761 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,12 @@ #include #include +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -140,6 +147,9 @@ void soc_init_pre_device(void *chip_info) itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); soc_fill_gpio_pm_configuration(); + + /* Swap enabled PCI ports in device tree if needed. */ + pcie_rp_update_devicetree(pch_lp_rp_groups); } static struct device_operations pci_domain_ops = { -- cgit v1.2.3