From 7e10c8209ba7a88639da82bd05584dbb9340bb83 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Tue, 13 Sep 2016 11:54:03 +0530 Subject: mainboards/apollolake: Set RAPL power limit PL1 value to 12W. This patch sets tuned RAPL power limit PL1 value to 12W in acpi/dptf.asl for RAPL MSR register. With PL1 as 12W for WebGL and stream case, we measured SoC power reaching upto 6W. Above 12W PL1 value, we observed that Soc power going above 6W. With PL1 as 12W, system is able to leverage full TDP capacity. BUG=chrome-os-partner:56524 TEST=Built, booted on reef and verifed the package power with heavy workload. Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/16596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/reef/acpi/dptf.asl | 2 +- src/mainboard/intel/amenia/acpi/dptf.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/reef/acpi/dptf.asl b/src/mainboard/google/reef/acpi/dptf.asl index 33d9b4d8f7..1f9bfb2f8b 100644 --- a/src/mainboard/google/reef/acpi/dptf.asl +++ b/src/mainboard/google/reef/acpi/dptf.asl @@ -73,7 +73,7 @@ Name (MPPC, Package () Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 1600, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ + 12000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 200 /* StepSize */ diff --git a/src/mainboard/intel/amenia/acpi/dptf.asl b/src/mainboard/intel/amenia/acpi/dptf.asl index 35bbecbfe7..a75d66839a 100644 --- a/src/mainboard/intel/amenia/acpi/dptf.asl +++ b/src/mainboard/intel/amenia/acpi/dptf.asl @@ -73,7 +73,7 @@ Name (MPPC, Package () Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 1600, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ + 12000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 200 /* StepSize */ -- cgit v1.2.3