From 7c5a9c7cb0cf6605435aa4c885c637273f9a0eee Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 6 Jul 2022 08:58:21 +0000 Subject: mb/google/rex: Refactor baseboard/variant gpio pad configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch tries to simplify the baseboard/variant GPIO programming starting with Google/Rex. The idea is to let each variant maintain its own complete GPIO PAD configuration table instead of having a back-and-forth call between baseboard and variants. With this patch coreboot performing GPIO programming is now much simpler where the common code block calls into respective variants and gets the gpio table prior to the pad configuration. BUG=b:238165977 (Simplify baseboard/variant GPIO programming starting with Google/Rex) TEST=Able to build and boot the Google/Rex board. AP firmware log with DEBUG_GPIO kconfig lists the early GPIOs being configured from the `rex0` variant. gpio_padcfg [0xd3, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020] gpio_padcfg [0xd3, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 09] DW1 [0x00000021 : 0x00000000 : 0x00000021] gpio_padcfg [0xd3, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000] Signed-off-by: Subrata Banik Change-Id: I8ec5c6991ec90a3884464e7f15f33327bfe4839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65674 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- .../google/rex/variants/baseboard/rex/Makefile.inc | 5 --- .../google/rex/variants/baseboard/rex/gpio.c | 47 ------------------- .../google/rex/variants/rex0/Makefile.inc | 3 ++ src/mainboard/google/rex/variants/rex0/gpio.c | 52 ++++++++++++++++++++++ 4 files changed, 55 insertions(+), 52 deletions(-) delete mode 100644 src/mainboard/google/rex/variants/baseboard/rex/gpio.c create mode 100644 src/mainboard/google/rex/variants/rex0/Makefile.inc create mode 100644 src/mainboard/google/rex/variants/rex0/gpio.c (limited to 'src') diff --git a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc index 7d1f88652d..fd45b948ff 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc +++ b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc @@ -1,6 +1 @@ -bootblock-y += gpio.c - -romstage-y += gpio.c romstage-y += memory.c - -ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c deleted file mode 100644 index 8ddd6cece0..0000000000 --- a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ - /* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ - PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), - /* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ - PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configuration */ - /* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ - PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), - /* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ - PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), -}; - -const struct pad_config *__weak variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *__weak variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -/* Create the stub for romstage gpio, typically use for power sequence */ -const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} - -static const struct cros_gpio cros_gpios[] = { -}; - -DECLARE_WEAK_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/rex/variants/rex0/Makefile.inc b/src/mainboard/google/rex/variants/rex0/Makefile.inc new file mode 100644 index 0000000000..2fa692abed --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c new file mode 100644 index 0000000000..c25cb25bdc --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* ToDo: Fill gpio configuration */ + /* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* ToDo: Fill early gpio configuration */ + /* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* ToDo: Fill romstage gpio configuration */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +DECLARE_WEAK_CROS_GPIOS(cros_gpios); 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