From 7b615f8eebb491e1d81db149089075612bbde14e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 29 Aug 2021 10:10:29 +0200 Subject: mb/intel/kblrvp: Do not use Legacy mode for UART #2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as coreboot console. However, the LPSS console driver requires the LPSS UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs). KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most likely results in the UART console not working after FSP-S has run. This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like the other KBLRVP variants do. Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 00690fa8c7..4bb00dd6ce 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -147,7 +147,7 @@ chip soc/intel/skylake [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ [PchSerialIoIndexUart0] = PchSerialIoPci, \ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" # PL2 override 25W -- cgit v1.2.3