From 7af59f709a89d20c1691d1a7316b136c7024aaf9 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 11 Jan 2020 13:53:10 -0500 Subject: sb/intel/i82371eb: Enable upper NVRAM bank Change-Id: I9ad127ca4394e27fc055ddf03012a195cb03bd94 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/38368 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/i82371eb/bootblock.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 711b317e16..581db816a8 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -61,4 +61,7 @@ void bootblock_early_southbridge_init(void) reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB; reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ pci_write_config16(dev, XBCS, reg16); + + /* Enable (RTC and) upper NVRAM bank. */ + pci_write_config8(dev, RTCCFG, RTC_POS_DECODE | UPPER_RAM_EN | RTC_ENABLE); } -- cgit v1.2.3