From 7a1e81a56f266179a2e8dee80bdf46ea74608807 Mon Sep 17 00:00:00 2001
From: Libra Li <libra.li@technexion.com>
Date: Wed, 18 Nov 2009 03:47:34 +0000
Subject: This is a patch to control the DIP switch and digital I/O.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
src/mainboard/technexion/tim5690/cache_as_ram_auto.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
(limited to 'src')
diff --git a/src/mainboard/technexion/tim5690/cache_as_ram_auto.c b/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
index e2817ab33f..9a8fccf3eb 100644
--- a/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
+++ b/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
@@ -145,6 +145,20 @@ fallback_image:
}
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+ /* Init Super I/O GPIOs. Done early. */
+ it8712f_enter_conf();
+ outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
+ outb(IT8712F_GPIO, SIO_DATA);
+ outb(0x62, SIO_INDEX); // set Simple I/O Base Address 0x200
+ outb(0x02, SIO_DATA);
+ outb(0x63, SIO_INDEX);
+ outb(0x00, SIO_DATA);
+ it8712f_exit_conf();
+}
+
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -177,6 +191,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+ mb_gpio_init();
it8712f_kill_watchdog();
uart_init();
console_init();
--
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