From 79e61603dc1e7c335a3e3f9c1f70b135cd8cfb96 Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Thu, 7 Apr 2022 15:07:46 +0200 Subject: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCH-S maps certain MMIO BARs differently than low power PCHs. The reserved ranges taken from Intel DOC #630603. Signed-off-by: Michał Żygowski Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63459 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/soc/intel/alderlake/include/soc/iomap.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 9ff8f54d01..4f692422db 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -12,11 +12,19 @@ /* * Memory-mapped I/O registers. */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_PRESERVED_BASE_ADDRESS 0xfe000000 +#define PCH_PRESERVED_BASE_SIZE 0x00800000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfd800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 +#else #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 +#endif #define UART_BASE_SIZE 0x1000 -- cgit v1.2.3