From 796bd74d632f9086029921280afd9ecb75c863af Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 4 Jan 2019 00:28:19 +0100 Subject: src/mb/apple/macbookair4_2: move early_southbridge.c to romstage.c This is done for consistency purposes. Also fix a small formatting issue in a function. Change-Id: I5dc170dbca59b7abbc912f9a26f76886b25ad82f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/30654 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick Reviewed-by: Felix Held --- src/mainboard/apple/macbookair4_2/Makefile.inc | 1 - .../apple/macbookair4_2/early_southbridge.c | 76 --------------------- src/mainboard/apple/macbookair4_2/romstage.c | 79 +++++++++++++++++++++- 3 files changed, 77 insertions(+), 79 deletions(-) delete mode 100644 src/mainboard/apple/macbookair4_2/early_southbridge.c (limited to 'src') diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index 555581cc4d..dd5eea3fd0 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -1,4 +1,3 @@ -romstage-y += early_southbridge.c romstage-y += gpio.c ramstage-y += gnvs.c diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c deleted file mode 100644 index 3ec61873b0..0000000000 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void pch_enable_lpc(void) -{ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); -} - -void mainboard_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; -} -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, -}; - -void mainboard_early_init(int s3resume) { -} - -void mainboard_config_superio(void) -{ -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - void *spd_file; - size_t spd_file_len = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (spd_file && spd_file_len >= 1024) { - int i; - for (i = 0; i < 4; i++) - memcpy(&spd[i], spd_file + 256 * i, 128); - } -} diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c index 78049bbd9e..914ee05866 100644 --- a/src/mainboard/apple/macbookair4_2/romstage.c +++ b/src/mainboard/apple/macbookair4_2/romstage.c @@ -1,2 +1,77 @@ -/* No license required */ -/* dummy file */ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); +} + +void mainboard_rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000020; +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 1024) { + int i; + for (i = 0; i < 4; i++) + memcpy(&spd[i], spd_file + 256 * i, 128); + } +} -- cgit v1.2.3