From 78f5c3b8c52443ebf1650aee194c320567a804d7 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 9 Sep 2024 10:30:10 +0100 Subject: mb/starlabs/starbook/adl: Alphabetize and group FSP UPDs Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/84261 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- .../starlabs/starbook/variants/adl/devicetree.cb | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index a555394214..5da7037e8a 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -1,22 +1,9 @@ chip soc/intel/alderlake - # Graphics - # TODO: - # register "panel_cfg" = "{ - # .up_delay_ms = 200, // T3 - # .backlight_on_delay_ms = 0, // T7 - # .backlight_off_delay_ms = 50, // T9 - # .down_delay_ms = 0, // T10 - # .cycle_delay_ms = 500, // T12 - # .backlight_pwm_hz = 200, // PWM - # }" - - # FSP Memory + # FSP UPDs + register "eist_enable" = "true" register "enable_c6dram" = "1" register "sagv" = "SaGv_Enabled" - # FSP Silicon - register "eist_enable" = "true" - # Serial I/O register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- cgit v1.2.3