From 7843bd560e65b0a83e99b42bdd58dd6363656c56 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:56:37 +0100 Subject: nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/intel/socket_LGA775/Kconfig | 4 + src/cpu/intel/socket_LGA775/Makefile.inc | 7 ++ src/mainboard/asrock/g41c-gs/Makefile.inc | 3 + src/mainboard/asrock/g41c-gs/early_init.c | 56 +++++++++ src/mainboard/asrock/g41c-gs/romstage.c | 55 --------- src/mainboard/asus/p5qc/Makefile.inc | 3 + src/mainboard/asus/p5qc/early_init.c | 41 +++++++ src/mainboard/asus/p5qc/romstage.c | 40 ------ src/mainboard/asus/p5ql-em/Makefile.inc | 3 + src/mainboard/asus/p5ql-em/early_init.c | 123 +++++++++++++++++++ src/mainboard/asus/p5ql-em/romstage.c | 122 ------------------ src/mainboard/asus/p5qpl-am/Makefile.inc | 3 + src/mainboard/asus/p5qpl-am/early_init.c | 143 ++++++++++++++++++++++ src/mainboard/asus/p5qpl-am/romstage.c | 142 --------------------- src/mainboard/foxconn/g41s-k/Makefile.inc | 3 + src/mainboard/foxconn/g41s-k/early_init.c | 63 ++++++++++ src/mainboard/foxconn/g41s-k/romstage.c | 62 ---------- src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc | 3 + src/mainboard/gigabyte/ga-g41m-es2l/early_init.c | 92 ++++++++++++++ src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 91 -------------- src/mainboard/intel/dg41wv/Makefile.inc | 3 + src/mainboard/intel/dg41wv/early_init.c | 48 ++++++++ src/mainboard/intel/dg41wv/romstage.c | 47 ------- src/mainboard/intel/dg43gt/Makefile.inc | 3 + src/mainboard/intel/dg43gt/early_init.c | 43 +++++++ src/mainboard/intel/dg43gt/romstage.c | 42 ------- src/mainboard/lenovo/thinkcentre_a58/Makefile.inc | 3 + src/mainboard/lenovo/thinkcentre_a58/early_init.c | 33 +++++ src/mainboard/lenovo/thinkcentre_a58/romstage.c | 32 ----- src/northbridge/intel/x4x/Kconfig | 5 +- src/northbridge/intel/x4x/Makefile.inc | 2 + src/northbridge/intel/x4x/bootblock.c | 8 +- src/northbridge/intel/x4x/romstage.c | 10 -- src/northbridge/intel/x4x/x4x.h | 1 - src/southbridge/intel/i82801jx/Kconfig | 5 - src/southbridge/intel/i82801jx/Makefile.inc | 3 + src/southbridge/intel/i82801jx/bootblock.c | 9 +- src/southbridge/intel/i82801jx/early_init.c | 2 +- src/southbridge/intel/i82801jx/i82801jx.h | 1 + 39 files changed, 696 insertions(+), 663 deletions(-) create mode 100644 src/mainboard/asrock/g41c-gs/early_init.c delete mode 100644 src/mainboard/asrock/g41c-gs/romstage.c create mode 100644 src/mainboard/asus/p5qc/early_init.c delete mode 100644 src/mainboard/asus/p5qc/romstage.c create mode 100644 src/mainboard/asus/p5ql-em/early_init.c delete mode 100644 src/mainboard/asus/p5ql-em/romstage.c create mode 100644 src/mainboard/asus/p5qpl-am/early_init.c delete mode 100644 src/mainboard/asus/p5qpl-am/romstage.c create mode 100644 src/mainboard/foxconn/g41s-k/early_init.c delete mode 100644 src/mainboard/foxconn/g41s-k/romstage.c create mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/early_init.c delete mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/romstage.c create mode 100644 src/mainboard/intel/dg41wv/early_init.c delete mode 100644 src/mainboard/intel/dg41wv/romstage.c create mode 100644 src/mainboard/intel/dg43gt/early_init.c delete mode 100644 src/mainboard/intel/dg43gt/romstage.c create mode 100644 src/mainboard/lenovo/thinkcentre_a58/early_init.c delete mode 100644 src/mainboard/lenovo/thinkcentre_a58/romstage.c (limited to 'src') diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd7e4..8db932ce58 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -19,6 +19,10 @@ config DCACHE_RAM_SIZE hex default 0x4000 # 16 kB +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + config DCACHE_RAM_BASE hex default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ceb084c900..a7984a9dfb 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,7 +13,14 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep +ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +else +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S +endif + postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc index 82e72fbb81..ab352cb73d 100644 --- a/src/mainboard/asrock/g41c-gs/Makefile.inc +++ b/src/mainboard/asrock/g41c-gs/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/g41c-gs/early_init.c b/src/mainboard/asrock/g41c-gs/early_init.c new file mode 100644 index 0000000000..c7c7b730a6 --- /dev/null +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) +#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +void bootblock_mainboard_early_init(void) +{ + /* Set GPIOs on superio, enable UART */ + if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { + nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); + pnp_set_logical_device(SERIAL_DEV_R2); + + pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80); + pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80); + pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60); + + nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); + nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); + } else { + winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); + } + /* IRQ routing */ + RCBA16(D31IR) = 0x0132; + RCBA16(D29IR) = 0x0237; +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c deleted file mode 100644 index 06e13eb652..0000000000 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) -#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) - -void mb_lpc_setup(void) -{ - /* Set GPIOs on superio, enable UART */ - if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { - nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); - pnp_set_logical_device(SERIAL_DEV_R2); - - pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80); - pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80); - pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60); - - nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); - nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); - } else { - winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); - } - /* IRQ routing */ - RCBA16(D31IR) = 0x0132; - RCBA16(D29IR) = 0x0237; -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} diff --git a/src/mainboard/asus/p5qc/Makefile.inc b/src/mainboard/asus/p5qc/Makefile.inc index 5c1d211ca7..88c57200d9 100644 --- a/src/mainboard/asus/p5qc/Makefile.inc +++ b/src/mainboard/asus/p5qc/Makefile.inc @@ -13,5 +13,8 @@ CONFIG_GPIO_C:=$(call strip_quotes, $(CONFIG_GPIO_C)) +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-y += cstates.c romstage-y += $(CONFIG_GPIO_C) diff --git a/src/mainboard/asus/p5qc/early_init.c b/src/mainboard/asus/p5qc/early_init.c new file mode 100644 index 0000000000..cbc84ba101 --- /dev/null +++ b/src/mainboard/asus/p5qc/early_init.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* TODO? */ + RCBA32(RCBA_CG) = 0xbf7f001f; + RCBA32(0x3430) = 0x00000002; + RCBA32(0x3f00) = 0x00000038; + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c deleted file mode 100644 index 53aa176b38..0000000000 --- a/src/mainboard/asus/p5qc/romstage.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) - -void mb_lpc_setup(void) -{ - /* TODO? */ - RCBA32(RCBA_CG) = 0xbf7f001f; - RCBA32(0x3430) = 0x00000002; - RCBA32(0x3f00) = 0x00000038; - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[1] = 0x51; - spd_map[2] = 0x52; - spd_map[3] = 0x53; -} diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc index 641e18f136..ba881b7eeb 100644 --- a/src/mainboard/asus/p5ql-em/Makefile.inc +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -11,6 +11,9 @@ # GNU General Public License for more details. # +bootblock-y += early_init.c + romstage-y += gpio.c +romstage-y += early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/early_init.c b/src/mainboard/asus/p5ql-em/early_init.c new file mode 100644 index 0000000000..38038012f7 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/early_init.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) + +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +static u8 msr_get_fsb(void) +{ + u8 fsbcfg; + msr_t msr; + const u32 eax = cpuid_eax(1); + + /* Netburst */ + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(MSR_EBC_FREQUENCY_ID); + fsbcfg = (msr.lo >> 16) & 0x7; + } else { /* Intel Core 2 */ + msr = rdmsr(MSR_FSB_FREQ); + fsbcfg = msr.lo & 0x7; + } + + return fsbcfg; +} + +/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */ +static int setup_sio_gpio(void) +{ + int need_reset = 0; + u8 reg, old_reg; + + u8 bsel = msr_get_fsb(); + switch (bsel) { + case 0: + case 2: + case 4: + break; + default: + printk(BIOS_WARNING, + "BSEL: Unsupported FSB frequency, using 800MHz\n"); + bsel = 2; /* 800MHz */ + break; + } + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + + /* + * P5QL-EM: + * BSEL0 -> not hooked up (not supported anyways) + * BSEL1 -> GPIO33 (inverted) + * BSEL2 -> GPIO40 + */ + reg = 0x92; + /* Multi-function Pin Selection */ + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + + pnp_write_config(GPIO_DEV, 0x30, 0x0e); /* Enable GPIO3x,4x,5x */ + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3x direction */ + pnp_write_config(GPIO_DEV, 0xf2, 0x08); /* GPIO3x inversion */ + pnp_write_config(GPIO_DEV, 0xf4, 0x06); /* GPIO4x direction */ + + const int gpio33 = (bsel & 2) >> 1; + const int gpio40 = (bsel & 4) >> 2; + reg = (gpio33 << 3); + old_reg = pnp_read_config(GPIO_DEV, 0xf1); /* GPIO3x data */ + /* Set GPIO32 high like vendor firmware */ + pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg | 4); + need_reset += ((reg & 0x8) != (old_reg & 0x8)); + + reg = gpio40; + old_reg = pnp_read_config(GPIO_DEV, 0xf5); /* GPIO4x data */ + pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); + need_reset += ((reg & 0x1) != (old_reg & 0x1)); + pnp_exit_ext_func_mode(GPIO_DEV); + + return need_reset; +} + +void mb_pre_raminit_setup(int s3_resume) +{ + if (!s3_resume && setup_sio_gpio()) { + printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); + full_reset(); + } +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups. So only the + first dimms of each channel are used. */ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c deleted file mode 100644 index fa22a645d4..0000000000 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) - -void mb_lpc_setup(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -static u8 msr_get_fsb(void) -{ - u8 fsbcfg; - msr_t msr; - const u32 eax = cpuid_eax(1); - - /* Netburst */ - if (((eax >> 8) & 0xf) == 0xf) { - msr = rdmsr(MSR_EBC_FREQUENCY_ID); - fsbcfg = (msr.lo >> 16) & 0x7; - } else { /* Intel Core 2 */ - msr = rdmsr(MSR_FSB_FREQ); - fsbcfg = msr.lo & 0x7; - } - - return fsbcfg; -} - -/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */ -static int setup_sio_gpio(void) -{ - int need_reset = 0; - u8 reg, old_reg; - - u8 bsel = msr_get_fsb(); - switch (bsel) { - case 0: - case 2: - case 4: - break; - default: - printk(BIOS_WARNING, - "BSEL: Unsupported FSB frequency, using 800MHz\n"); - bsel = 2; /* 800MHz */ - break; - } - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - - /* - * P5QL-EM: - * BSEL0 -> not hooked up (not supported anyways) - * BSEL1 -> GPIO33 (inverted) - * BSEL2 -> GPIO40 - */ - reg = 0x92; - /* Multi-function Pin Selection */ - old_reg = pnp_read_config(GPIO_DEV, 0x2c); - pnp_write_config(GPIO_DEV, 0x2c, reg); - need_reset = (reg != old_reg); - - pnp_write_config(GPIO_DEV, 0x30, 0x0e); /* Enable GPIO3x,4x,5x */ - pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3x direction */ - pnp_write_config(GPIO_DEV, 0xf2, 0x08); /* GPIO3x inversion */ - pnp_write_config(GPIO_DEV, 0xf4, 0x06); /* GPIO4x direction */ - - const int gpio33 = (bsel & 2) >> 1; - const int gpio40 = (bsel & 4) >> 2; - reg = (gpio33 << 3); - old_reg = pnp_read_config(GPIO_DEV, 0xf1); /* GPIO3x data */ - /* Set GPIO32 high like vendor firmware */ - pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg | 4); - need_reset += ((reg & 0x8) != (old_reg & 0x8)); - - reg = gpio40; - old_reg = pnp_read_config(GPIO_DEV, 0xf5); /* GPIO4x data */ - pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); - need_reset += ((reg & 0x1) != (old_reg & 0x1)); - pnp_exit_ext_func_mode(GPIO_DEV); - - return need_reset; -} - -void mb_pre_raminit_setup(int s3_resume) -{ - if (!s3_resume && setup_sio_gpio()) { - printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); - full_reset(); - } -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - /* This board has first dimm slot of each channel hooked up to - rank0 and rank1, while the second dimm slot is only connected - to rank1. The raminit does not support such setups. So only the - first dimms of each channel are used. */ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} diff --git a/src/mainboard/asus/p5qpl-am/Makefile.inc b/src/mainboard/asus/p5qpl-am/Makefile.inc index 82e72fbb81..ab352cb73d 100644 --- a/src/mainboard/asus/p5qpl-am/Makefile.inc +++ b/src/mainboard/asus/p5qpl-am/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5qpl-am/early_init.c b/src/mainboard/asus/p5qpl-am/early_init.c new file mode 100644 index 0000000000..5987033a09 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/early_init.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) + +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +static u8 msr_get_fsb(void) +{ + u8 fsbcfg; + msr_t msr; + const u32 eax = cpuid_eax(1); + + /* Netburst */ + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(MSR_EBC_FREQUENCY_ID); + fsbcfg = (msr.lo >> 16) & 0x7; + } else { /* Intel Core 2 */ + msr = rdmsr(MSR_FSB_FREQ); + fsbcfg = msr.lo & 0x7; + } + + return fsbcfg; +} + +/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */ + +static int setup_sio_gpio(void) +{ + int need_reset = 0; + u8 reg, old_reg; + + u8 bsel = msr_get_fsb(); + switch (bsel) { + case 0: + case 2: + case 4: + break; + default: + printk(BIOS_WARNING, + "BSEL: Unsupported FSB frequency, using 800MHz\n"); + bsel = 2; /* 800MHz */ + break; + } + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + + if (CONFIG(BOARD_ASUS_P5QPL_AM)) { + /* + * P5QPL-AM: + * BSEL0 -> not hooked up (not supported anyways) + * BSEL1 -> GPIO33 + * BSEL2 -> GPIO40 + */ + reg = 0x92; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + + pnp_write_config(GPIO_DEV, 0x30, 0x06); + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3 direction */ + pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ + + const int gpio33 = (bsel & 2) >> 1; + const int gpio40 = (bsel & 4) >> 2; + reg = (gpio33 << 3); + old_reg = pnp_read_config(GPIO_DEV, 0xf1); + pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg); + need_reset += ((reg & 0x8) != (old_reg & 0x8)); + + reg = gpio40; + old_reg = pnp_read_config(GPIO_DEV, 0xf5); + pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); + need_reset += ((reg & 0x1) != (old_reg & 0x1)); + } else { + /* + * P5G41T-M LX: + * BSEL0 -> not hooked up + * BSEL1 -> GPIO43 (inverted) + * BSEL2 -> GPIO44 + */ + reg = 0xf2; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + pnp_write_config(GPIO_DEV, 0x30, 0x05); + pnp_write_config(GPIO_DEV, 0xf6, 0x08); /* invert GPIO43 */ + pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ + + const int gpio43 = (bsel & 2) >> 1; + const int gpio44 = (bsel & 4) >> 2; + reg = (gpio43 << 3) | (gpio44 << 4); + old_reg = pnp_read_config(GPIO_DEV, 0xf5); + pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); + need_reset += ((reg & 0x18) != (old_reg & 0x18)); + } + pnp_exit_ext_func_mode(GPIO_DEV); + + return need_reset; +} + +void mb_pre_raminit_setup(int s3_resume) +{ + if (!s3_resume && setup_sio_gpio()) { + printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); + full_reset(); + } +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c deleted file mode 100644 index ad16c0f72a..0000000000 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) - -void mb_lpc_setup(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -static u8 msr_get_fsb(void) -{ - u8 fsbcfg; - msr_t msr; - const u32 eax = cpuid_eax(1); - - /* Netburst */ - if (((eax >> 8) & 0xf) == 0xf) { - msr = rdmsr(MSR_EBC_FREQUENCY_ID); - fsbcfg = (msr.lo >> 16) & 0x7; - } else { /* Intel Core 2 */ - msr = rdmsr(MSR_FSB_FREQ); - fsbcfg = msr.lo & 0x7; - } - - return fsbcfg; -} - -/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */ - -static int setup_sio_gpio(void) -{ - int need_reset = 0; - u8 reg, old_reg; - - u8 bsel = msr_get_fsb(); - switch (bsel) { - case 0: - case 2: - case 4: - break; - default: - printk(BIOS_WARNING, - "BSEL: Unsupported FSB frequency, using 800MHz\n"); - bsel = 2; /* 800MHz */ - break; - } - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - - if (CONFIG(BOARD_ASUS_P5QPL_AM)) { - /* - * P5QPL-AM: - * BSEL0 -> not hooked up (not supported anyways) - * BSEL1 -> GPIO33 - * BSEL2 -> GPIO40 - */ - reg = 0x92; - old_reg = pnp_read_config(GPIO_DEV, 0x2c); - pnp_write_config(GPIO_DEV, 0x2c, reg); - need_reset = (reg != old_reg); - - pnp_write_config(GPIO_DEV, 0x30, 0x06); - pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3 direction */ - pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ - - const int gpio33 = (bsel & 2) >> 1; - const int gpio40 = (bsel & 4) >> 2; - reg = (gpio33 << 3); - old_reg = pnp_read_config(GPIO_DEV, 0xf1); - pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg); - need_reset += ((reg & 0x8) != (old_reg & 0x8)); - - reg = gpio40; - old_reg = pnp_read_config(GPIO_DEV, 0xf5); - pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); - need_reset += ((reg & 0x1) != (old_reg & 0x1)); - } else { - /* - * P5G41T-M LX: - * BSEL0 -> not hooked up - * BSEL1 -> GPIO43 (inverted) - * BSEL2 -> GPIO44 - */ - reg = 0xf2; - old_reg = pnp_read_config(GPIO_DEV, 0x2c); - pnp_write_config(GPIO_DEV, 0x2c, reg); - need_reset = (reg != old_reg); - pnp_write_config(GPIO_DEV, 0x30, 0x05); - pnp_write_config(GPIO_DEV, 0xf6, 0x08); /* invert GPIO43 */ - pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ - - const int gpio43 = (bsel & 2) >> 1; - const int gpio44 = (bsel & 4) >> 2; - reg = (gpio43 << 3) | (gpio44 << 4); - old_reg = pnp_read_config(GPIO_DEV, 0xf5); - pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); - need_reset += ((reg & 0x18) != (old_reg & 0x18)); - } - pnp_exit_ext_func_mode(GPIO_DEV); - - return need_reset; -} - -void mb_pre_raminit_setup(int s3_resume) -{ - if (!s3_resume && setup_sio_gpio()) { - printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); - full_reset(); - } -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} diff --git a/src/mainboard/foxconn/g41s-k/Makefile.inc b/src/mainboard/foxconn/g41s-k/Makefile.inc index ca8de4d597..161c623eaa 100644 --- a/src/mainboard/foxconn/g41s-k/Makefile.inc +++ b/src/mainboard/foxconn/g41s-k/Makefile.inc @@ -1,6 +1,9 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/ diff --git a/src/mainboard/foxconn/g41s-k/early_init.c b/src/mainboard/foxconn/g41s-k/early_init.c new file mode 100644 index 0000000000..454b1ea0b0 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/early_init.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2017 Arthur Heymans + * Copyright (C) 2017 Samuel Holland + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIOs on Super I/O. */ + ite_reg_write(GPIO_DEV, 0x25, 0x01); + ite_reg_write(GPIO_DEV, 0x26, 0x04); + ite_reg_write(GPIO_DEV, 0x27, 0x00); + ite_reg_write(GPIO_DEV, 0x28, 0x40); + ite_reg_write(GPIO_DEV, 0x29, 0x01); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0x74, 0x00); + ite_reg_write(GPIO_DEV, 0xb1, 0x04); + ite_reg_write(GPIO_DEV, 0xb8, 0x20); + ite_reg_write(GPIO_DEV, 0xbb, 0x01); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xcb, 0x01); + ite_reg_write(GPIO_DEV, 0xf5, 0x28); + ite_reg_write(GPIO_DEV, 0xf6, 0x12); + ite_enable_3vsbsw(GPIO_DEV); + + /* Set up IRQ routing. */ + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x3241; + RCBA16(D29IR) = 0x0237; + + RCBA32(FD) |= FD_INTLAN; + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + if (CONFIG(BOARD_FOXCONN_G41M)) + spd_map[2] = 0x52; +} diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c deleted file mode 100644 index b4bd77d78b..0000000000 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * Copyright (C) 2017 Samuel Holland - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) - -void mb_lpc_setup(void) -{ - /* Set up GPIOs on Super I/O. */ - ite_reg_write(GPIO_DEV, 0x25, 0x01); - ite_reg_write(GPIO_DEV, 0x26, 0x04); - ite_reg_write(GPIO_DEV, 0x27, 0x00); - ite_reg_write(GPIO_DEV, 0x28, 0x40); - ite_reg_write(GPIO_DEV, 0x29, 0x01); - ite_reg_write(GPIO_DEV, 0x73, 0x00); - ite_reg_write(GPIO_DEV, 0x74, 0x00); - ite_reg_write(GPIO_DEV, 0xb1, 0x04); - ite_reg_write(GPIO_DEV, 0xb8, 0x20); - ite_reg_write(GPIO_DEV, 0xbb, 0x01); - ite_reg_write(GPIO_DEV, 0xc0, 0x00); - ite_reg_write(GPIO_DEV, 0xc3, 0x01); - ite_reg_write(GPIO_DEV, 0xcb, 0x01); - ite_reg_write(GPIO_DEV, 0xf5, 0x28); - ite_reg_write(GPIO_DEV, 0xf6, 0x12); - ite_enable_3vsbsw(GPIO_DEV); - - /* Set up IRQ routing. */ - RCBA16(D31IR) = 0x0132; - RCBA16(D30IR) = 0x3241; - RCBA16(D29IR) = 0x0237; - - RCBA32(FD) |= FD_INTLAN; - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - if (CONFIG(BOARD_FOXCONN_G41M)) - spd_map[2] = 0x52; -} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c new file mode 100644 index 0000000000..4540d4e03d --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +void bootblock_mainboard_early_init(void) +{ + pci_devfn_t dev; + + /* Southbridge GPIOs. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xc7); + ite_reg_write(GPIO_DEV, 0x27, 0x80); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x0a); + ite_reg_write(GPIO_DEV, 0x2c, 0x01); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x72, 0x00); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0xb8, 0x00); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc1, 0xc7); + ite_reg_write(GPIO_DEV, 0xc2, 0x80); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xc4, 0x0a); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x04); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xcc, 0x02); + ite_reg_write(GPIO_DEV, 0xf0, 0x10); + ite_reg_write(GPIO_DEV, 0xf1, 0x40); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x52); + + ite_reg_write(EC_DEV, 0xf0, 0x80); + ite_reg_write(EC_DEV, 0xf1, 0x00); + ite_reg_write(EC_DEV, 0xf2, 0x0a); + ite_reg_write(EC_DEV, 0xf3, 0x80); + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + ite_reg_write(EC_DEV, 0x30, 0x01); // Enable + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + + /* IRQ routing */ + RCBA32(D31IP) = 0x00002210; + RCBA32(D30IP) = 0x00002100; + RCBA32(D29IP) = 0x10004321; + RCBA32(D28IP) = 0x00214321; + RCBA32(D27IP) = 0x00000001; + RCBA32(D31IR) = 0x00410032; + RCBA32(D29IR) = 0x32100237; + RCBA32(D27IR) = 0x00000000; +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c deleted file mode 100644 index bde4f33bef..0000000000 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) - -/* Early mainboard specific GPIO setup. - * We should use standard gpio.h eventually - */ - -void mb_lpc_setup(void) -{ - pci_devfn_t dev; - - /* Southbridge GPIOs. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); - /* Set default GPIOs on superio */ - ite_reg_write(GPIO_DEV, 0x25, 0x00); - ite_reg_write(GPIO_DEV, 0x26, 0xc7); - ite_reg_write(GPIO_DEV, 0x27, 0x80); - ite_reg_write(GPIO_DEV, 0x28, 0x41); - ite_reg_write(GPIO_DEV, 0x29, 0x0a); - ite_reg_write(GPIO_DEV, 0x2c, 0x01); - ite_reg_write(GPIO_DEV, 0x62, 0x08); - ite_reg_write(GPIO_DEV, 0x72, 0x00); - ite_reg_write(GPIO_DEV, 0x73, 0x00); - ite_reg_write(GPIO_DEV, 0xb8, 0x00); - ite_reg_write(GPIO_DEV, 0xbb, 0x40); - ite_reg_write(GPIO_DEV, 0xc0, 0x00); - ite_reg_write(GPIO_DEV, 0xc1, 0xc7); - ite_reg_write(GPIO_DEV, 0xc2, 0x80); - ite_reg_write(GPIO_DEV, 0xc3, 0x01); - ite_reg_write(GPIO_DEV, 0xc4, 0x0a); - ite_reg_write(GPIO_DEV, 0xc8, 0x00); - ite_reg_write(GPIO_DEV, 0xc9, 0x04); - ite_reg_write(GPIO_DEV, 0xcb, 0x00); - ite_reg_write(GPIO_DEV, 0xcc, 0x02); - ite_reg_write(GPIO_DEV, 0xf0, 0x10); - ite_reg_write(GPIO_DEV, 0xf1, 0x40); - ite_reg_write(GPIO_DEV, 0xf6, 0x26); - ite_reg_write(GPIO_DEV, 0xfc, 0x52); - - ite_reg_write(EC_DEV, 0xf0, 0x80); - ite_reg_write(EC_DEV, 0xf1, 0x00); - ite_reg_write(EC_DEV, 0xf2, 0x0a); - ite_reg_write(EC_DEV, 0xf3, 0x80); - ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 - ite_reg_write(EC_DEV, 0x30, 0x01); // Enable - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Disable SIO reboot */ - ite_reg_write(GPIO_DEV, 0xEF, 0x7E); - - /* IRQ routing */ - RCBA32(D31IP) = 0x00002210; - RCBA32(D30IP) = 0x00002100; - RCBA32(D29IP) = 0x10004321; - RCBA32(D28IP) = 0x00214321; - RCBA32(D27IP) = 0x00000001; - RCBA32(D31IR) = 0x00410032; - RCBA32(D29IR) = 0x32100237; - RCBA32(D27IR) = 0x00000000; -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} diff --git a/src/mainboard/intel/dg41wv/Makefile.inc b/src/mainboard/intel/dg41wv/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/intel/dg41wv/Makefile.inc +++ b/src/mainboard/intel/dg41wv/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg41wv/early_init.c b/src/mainboard/intel/dg41wv/early_init.c new file mode 100644 index 0000000000..3cb40955d0 --- /dev/null +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Set GPIOs on superio, enable UART */ + pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_set_logical_device(SERIAL_DEV); + + pnp_write_config(SERIAL_DEV, 0x2c, 0x13); + + pnp_exit_ext_func_mode(SERIAL_DEV); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* IRQ routing */ + RCBA16(D31IR) = 0x0132; + RCBA16(D29IR) = 0x0237; +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c deleted file mode 100644 index ff018af5f6..0000000000 --- a/src/mainboard/intel/dg41wv/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) - -void mb_lpc_setup(void) -{ - /* Set GPIOs on superio, enable UART */ - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_set_logical_device(SERIAL_DEV); - - pnp_write_config(SERIAL_DEV, 0x2c, 0x13); - - pnp_exit_ext_func_mode(SERIAL_DEV); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* IRQ routing */ - RCBA16(D31IR) = 0x0132; - RCBA16(D29IR) = 0x0237; -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} diff --git a/src/mainboard/intel/dg43gt/Makefile.inc b/src/mainboard/intel/dg43gt/Makefile.inc index 6b3d94a037..f89d1302e3 100644 --- a/src/mainboard/intel/dg43gt/Makefile.inc +++ b/src/mainboard/intel/dg43gt/Makefile.inc @@ -14,4 +14,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg43gt/early_init.c b/src/mainboard/intel/dg43gt/early_init.c new file mode 100644 index 0000000000..8457707ba1 --- /dev/null +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) + +void bootblock_mainboard_early_init(void) +{ + RCBA32(0x3410) = 0x00060464; + RCBA32(RCBA_BUC) &= ~BUC_LAND; + RCBA32(0x3418) = 0x01320001; + RCBA32(0x341c) = 0xbf7f001f; + RCBA32(0x3430) = 0x00000002; + RCBA32(0x3f00) = 0x0000000b; + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c deleted file mode 100644 index 71fd87ad74..0000000000 --- a/src/mainboard/intel/dg43gt/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) - -void mb_lpc_setup(void) -{ - RCBA32(0x3410) = 0x00060464; - RCBA32(RCBA_BUC) &= ~BUC_LAND; - RCBA32(0x3418) = 0x01320001; - RCBA32(0x341c) = 0xbf7f001f; - RCBA32(0x3430) = 0x00000002; - RCBA32(0x3f00) = 0x0000000b; - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[1] = 0x51; - spd_map[2] = 0x52; - spd_map[3] = 0x53; -} diff --git a/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc b/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc +++ b/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/thinkcentre_a58/early_init.c b/src/mainboard/lenovo/thinkcentre_a58/early_init.c new file mode 100644 index 0000000000..a8f6443948 --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_a58/early_init.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +void bootblock_mainboard_early_init(void) +{ + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; +} diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c deleted file mode 100644 index 5594cbdda6..0000000000 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -void mb_lpc_setup(void) -{ - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x52; -} diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8f002c6a8f..2a54e2495e 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,15 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select C_ENVIRONMENT_BOOTBLOCK config CBFS_SIZE hex default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/x4x/bootblock.c" - config VGA_BIOS_ID string default "8086,2e32" diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 79a03cb77e..cde7121f93 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -16,6 +16,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) +bootblock-y += bootblock.c + romstage-y += early_init.c romstage-y += raminit.c romstage-y += raminit_ddr23.c diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index e733287e93..64643dd79c 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -15,13 +15,11 @@ */ #include +#include +#include "x4x.h" #include "iomap.h" -/* Just re-define these instead of including x4x.h. It blows up romcc. */ -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg32; diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index c3a503643f..eae87f3674 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -34,16 +34,6 @@ void mainboard_romstage_entry(void) u8 boot_path = 0; u8 s3_resume; -#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) - i82801jx_lpc_setup(); -#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) - i82801gx_lpc_setup(); -#endif - - mb_lpc_setup(); - - console_init(); - enable_smbus(); #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index e4a6c215d8..aaaa28aeac 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -373,7 +373,6 @@ enum ddr2_signals { void x4x_early_init(void); void x4x_late_init(int s3resume); -void mb_lpc_setup(void); void mb_get_spd_map(u8 spd_map[4]); void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index eeb843e910..7f44fcfc1d 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -51,9 +51,4 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED config HPET_MIN_TICKS hex default 0x80 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801jx/bootblock.c" - endif diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 30ed351970..1527b8adb0 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -16,6 +16,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) +bootblock-y += bootblock.c +bootblock-y += early_init.c + ramstage-y += i82801jx.c ramstage-y += pci.c ramstage-y += lpc.c diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 01faef34af..b6016793c2 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,6 +14,7 @@ */ #include +#include #include "i82801jx.h" static void enable_spi_prefetch(void) @@ -29,14 +30,14 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + i82801jx_setup_bars(); /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); + + i82801jx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 469073240e..1afc6b365f 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -56,7 +56,7 @@ void i82801jx_lpc_setup(void) pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); } -static void i82801jx_setup_bars(void) +void i82801jx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index d406d1d631..26a99f42f7 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -235,6 +235,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif void i82801jx_lpc_setup(void); +void i82801jx_setup_bars(void); void i82801jx_early_init(void); #endif -- cgit v1.2.3