From 77133afe3142096cc7ea7755bfc727f59f2282f9 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 1 Jan 2016 23:30:42 -0600 Subject: sb/amd/sr5650: Correctly locate CPU MMCONFIG resource The code committed in GIT hash * 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support did not correctly locate the CPU MMCONFIG resource, leading to failures with operating systems and firmware (e.g. SeaBIOS) when the PCI extended configuration space option was activated. Due to the southbridge routing not being set up, MMCONFIG accesses were targetting DRAM and therefore the PCI devices were not being configured. The failure normally manifests as a system hang immediately after PCI configuration starts. Search for the CPU MMCONFIG resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/12821 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Alexandru Gagniuc --- src/southbridge/amd/sr5650/sr5650.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d4355d6861..818b0e646c 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -35,13 +35,13 @@ extern void set_pcie_dereset(void); extern void set_pcie_reset(void); struct resource * sr5650_retrieve_cpu_mmio_resource() { - device_t cpu; + device_t domain; struct resource *res; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) + for (domain = all_devices; domain; domain = domain->next) { + if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) continue; - res = probe_resource(cpu->bus->dev, 0xc0010058); + res = probe_resource(domain->bus->dev, 0xc0010058); if (res) return res; } -- cgit v1.2.3