From 757571eec16295d66a8c06033a61b73bad9c06fa Mon Sep 17 00:00:00 2001
From: Shelley Chen <shchen@google.com>
Date: Tue, 29 Jan 2019 15:30:14 -0800
Subject: mb/google/hatch: Enable S0ix

BUG=b:123540469
BRANCH=None
TEST=None

Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31157
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src')

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index cea64e4237..2bc4f785a8 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -55,6 +55,8 @@ chip soc/intel/cannonlake
 	register "HeciEnabled" = "1"
 	# Enable Speed Shift Technology support
 	register "speed_shift_enable" = "1"
+	# Enable S0ix
+	register "s0ix_enable" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 1
-- 
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