From 75154b801f8c31298125d4fc0a3ee069058dc0b6 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Thu, 9 Jul 2015 18:00:40 +0530 Subject: kunimitsu: Update Serial IO modes in devicetree This patch updates the Serial IO modes for UART 1 and 2 in devicetree for kunimitsu boards. UART1 are disabled and UART2 is in PCI mode. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for kunimitsu and tested LPSS logs on Kunimitsu. Change-Id: I5a46ab9e0b792478ee2e0845aeab1443423a2fac Signed-off-by: Patrick Georgi Original-Commit-Id: 38c7b963a9d679ee5106c5343e1173d0b5056627 Original-Change-Id: I39cbb6bb0991e5f9b3365adaf6b24818d112cd1a Original-Signed-off-by: Naveen Krishna Chatradhi Original-Reviewed-on: https://chromium-review.googlesource.com/284825 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Wenkai Du Original-Tested-by: Wenkai Du Reviewed-on: http://review.coreboot.org/11001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/intel/kunimitsu/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index f1530829bc..9b0ca0ff78 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/skylake [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ [PchSerialIoIndexUart0] = PchSerialIoPci, \ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ }" register "pirqa_routing" = "0x8b" -- cgit v1.2.3