From 73ae076e954ea6acd2fd22386616cd4ce839c830 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 10:13:05 +0200 Subject: sb/intel/lynxpoint: Fix 16-bit read/write PCI_COMMAND register Change-Id: I81b740e0cfcf0e1bf096427b45ffba06d357fee6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40792 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/lynxpoint/azalia.c | 4 +--- src/southbridge/intel/lynxpoint/early_usb.c | 5 +---- src/southbridge/intel/lynxpoint/me_9.x.c | 13 +++++-------- src/southbridge/intel/lynxpoint/pch.c | 13 +++++-------- src/southbridge/intel/lynxpoint/pcie.c | 18 ++++++------------ src/southbridge/intel/lynxpoint/serialio.c | 5 +---- src/southbridge/intel/lynxpoint/smihandler.c | 8 ++++---- src/southbridge/intel/lynxpoint/usb_ehci.c | 9 ++++----- 8 files changed, 27 insertions(+), 48 deletions(-) (limited to 'src') diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index cbdd3f6ee9..cc77956b54 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -116,7 +116,6 @@ static void azalia_init(struct device *dev) u8 *base; struct resource *res; u32 codec_mask; - u32 reg32; /* Find base address */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -127,8 +126,7 @@ static void azalia_init(struct device *dev) printk(BIOS_DEBUG, "Azalia: base = %p\n", base); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); azalia_pch_init(dev, base); diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 2f28369d53..075892b580 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -25,11 +25,8 @@ */ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { - u32 cmd; pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); - cmd = pci_read_config32(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, cmd); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } void enable_usb_bar(void) diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index c5562c5cfc..4599c26cff 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -568,6 +568,7 @@ void intel_me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; + u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -595,10 +596,9 @@ void intel_me_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -726,7 +726,6 @@ static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; - u32 reg32; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -737,9 +736,7 @@ static int intel_mei_setup(struct device *dev) mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index a09f28e7a7..b8060a22dd 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -286,7 +286,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) void pch_enable(struct device *dev) { - u32 reg32; + u16 reg16; /* PCH PCIe Root Ports are handled in PCIe driver. */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) @@ -296,18 +296,15 @@ void pch_enable(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 0ca49b802c..3daf1826a5 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -277,7 +277,7 @@ static void root_port_commit_config(void) for (i = 0; i < rpc.num_ports; i++) { struct device *dev; - u32 reg32; + u16 reg16; dev = rpc.ports[i]; @@ -292,10 +292,9 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -654,19 +653,14 @@ static void pch_pcie_early(struct device *dev) static void pci_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 4591566e1b..f789e7c784 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -134,14 +134,11 @@ static void serialio_init(struct device *dev) struct southbridge_intel_lynxpoint_config *config = dev->chip_info; struct resource *bar0, *bar1; int sio_index = -1; - u32 reg32; printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index e156b347c1..427c4fb337 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -64,7 +64,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -74,9 +74,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index ce81f76f44..1fde466eb7 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -16,7 +16,6 @@ void usb_ehci_disable(pci_devfn_t dev) { u16 reg16; - u32 reg32; /* Set 0xDC[0]=1 */ pci_or_config32(dev, 0xdc, (1 << 0)); @@ -29,9 +28,9 @@ void usb_ehci_disable(pci_devfn_t dev) /* Clear memory and bus master */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable device */ switch (dev) { @@ -56,7 +55,7 @@ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff) return; - pci_cmd = pci_read_config32(dev, PCI_COMMAND); + pci_cmd = pci_read_config16(dev, PCI_COMMAND); switch (slp_typ) { case ACPI_S4: -- cgit v1.2.3