From 6ee6bdec258bcd76ee690a20856a3d7e79b31a04 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 1 Jun 2015 20:35:42 -0500 Subject: amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33 Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/11969 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 80a85ff604..f4bf402775 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1848,11 +1848,13 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, if (nv_DQSTrainCTL) { mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); - /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(0x26C, 0x04040404, 0x04040404); - _WRMSR(0x26D, 0x04040404, 0x04040404); - _WRMSR(0x26E, 0x04040404, 0x04040404); - _WRMSR(0x26F, 0x04040404, 0x04040404); + if (!is_fam15h()) { + /* TODO: should be in mctHookBeforeAnyTraining */ + _WRMSR(0x26C, 0x04040404, 0x04040404); + _WRMSR(0x26D, 0x04040404, 0x04040404); + _WRMSR(0x26E, 0x04040404, 0x04040404); + _WRMSR(0x26F, 0x04040404, 0x04040404); + } mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); if (is_fam15h()) { -- cgit v1.2.3