From 6e82ebff73d0a2a9d29248885b30384f1f550376 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 31 Jan 2021 15:15:11 +0100 Subject: mb/ocp/deltalake: Fill ECC type in romstage Fill the ECC type in `struct memory_info` in romstage, and in SoC code. The SMBIOS override is unnecessary, and this is not mainboard-specific. Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179 Reviewed-by: Paul Menzel Reviewed-by: Johnny Lin Reviewed-by: Patrick Rudolph Reviewed-by: Jonathan Zhang Tested-by: build bot (Jenkins) --- src/arch/x86/smbios.c | 7 +------ src/include/smbios.h | 1 - src/mainboard/ocp/deltalake/ramstage.c | 25 ------------------------- src/soc/intel/xeon_sp/cpx/romstage.c | 20 ++++++++++++++++++++ 4 files changed, 21 insertions(+), 32 deletions(-) (limited to 'src') diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index bd7f4224ec..33ab1ba3fe 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -443,11 +443,6 @@ static int get_socket_type(void) return 0x02; /* Unknown */ } -unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo) -{ - return meminfo->ecc_type; -} - unsigned int __weak smbios_processor_external_clock(void) { return 0; /* Unknown */ @@ -1023,7 +1018,7 @@ static int smbios_write_type16(unsigned long *current, int *handle) t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; t->use = MEMORY_ARRAY_USE_SYSTEM; - t->memory_error_correction = smbios_memory_error_correction_type(meminfo); + t->memory_error_correction = meminfo->ecc_type; /* no error information handle available */ t->memory_error_information_handle = 0xFFFE; diff --git a/src/include/smbios.h b/src/include/smbios.h index 91f031ae94..78f364e336 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -61,7 +61,6 @@ void smbios_type0_bios_version(uintptr_t address); void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); -unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo); unsigned int smbios_processor_external_clock(void); unsigned int smbios_processor_characteristics(void); struct cpuid_result; diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index dc70eb23b2..7c79949a6c 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -23,31 +23,6 @@ extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; -/* Override SMBIOS type 16 error correction type. */ -unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo) -{ - const struct SystemMemoryMapHob *hob; - - hob = get_system_memory_map(); - assert(hob != NULL); - - switch (hob->RasModesEnabled) { - case CH_INDEPENDENT: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - case FULL_MIRROR_1LM: - case PARTIAL_MIRROR_1LM: - case FULL_MIRROR_2LM: - case PARTIAL_MIRROR_2LM: - return MEMORY_ARRAY_ECC_MULTI_BIT; - case RK_SPARE: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - case CH_LOCKSTEP: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - default: - return MEMORY_ARRAY_ECC_MULTI_BIT; - } -} - /* * Update SMBIOS type 0 ec version. * In deltalake, BMC version is used to represent ec version. diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 6025f2a6d0..c1cb0caeea 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -37,6 +37,25 @@ static const struct SystemMemoryMapHob *get_system_memory_map(void) return *memmap_addr; } +static uint8_t get_error_correction_type(const uint8_t RasModesEnabled) +{ + switch (RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + /* Save the DIMM information for SMBIOS table 17 */ void save_dimm_info(void) { @@ -63,6 +82,7 @@ void save_dimm_info(void) /* According to Dear Customer Letter it's 1.12 TB per processor. */ mem_info->max_capacity_mib = 1.12 * MiB * CONFIG_MAX_SOCKET; mem_info->number_of_devices = CONFIG_DIMM_MAX; + mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled); dimm_max = ARRAY_SIZE(mem_info->dimm); vdd_voltage = get_ddr_voltage(hob->DdrVoltage); /* For now only implement for one socket and hard-coded for DDR4 */ -- cgit v1.2.3