From 6e37b0acb6b760352fe3aa5905a6234ac7969e5b Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 17 Apr 2017 06:45:56 +0300 Subject: binaryPI: Enable EARLY_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also moves postcar stack to CBMEM. Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/19347 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) Reviewed-by: Ricardo Ribalda Delgado Reviewed-by: Philippe Mathieu-Daudé --- src/cpu/amd/pi/romstage.c | 12 +++++++++++- src/northbridge/amd/pi/Kconfig | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index 393cbd4aeb..9a5fbac003 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -14,10 +14,12 @@ */ #include +#include #include #include #include #include +#include #include #include @@ -28,12 +30,20 @@ void asmlinkage early_all_cores(void) void * asmlinkage romstage_main(unsigned long bist) { - uintptr_t stack_top = CACHE_TMP_RAMTOP; + int s3resume = 0; u8 initial_apic_id = cpuid_ebx(1) >> 24; /* Only BSP returns from here. */ cache_as_ram_main(bist, initial_apic_id); + cbmem_recovery(s3resume); + + romstage_handoff_init(s3resume); + + uintptr_t stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + stack_top += HIGH_ROMSTAGE_STACK_SIZE; + printk(BIOS_DEBUG, "Move CAR stack.\n"); return (void*)stack_top; } diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 6f4c4b73be..7da2ae9e64 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -17,7 +17,7 @@ config NORTHBRIDGE_AMD_PI bool default y if CPU_AMD_PI default n - select LATE_CBMEM_INIT + select CBMEM_TOP_BACKUP if NORTHBRIDGE_AMD_PI -- cgit v1.2.3