From 6c3ad1341f3532e0ac4c20d6e7a049a53ee1c724 Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Sat, 17 Jul 2021 00:02:23 +0530 Subject: soc/qualcomm/common/spi: Configure SPI QUP driver This implements the SPI driver for the QUP core. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil Change-Id: I7e5d3ad07f68255727958d53e6919944d3038260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56399 Reviewed-by: Shelley Chen Tested-by: build bot (Jenkins) --- src/soc/qualcomm/common/spi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src') diff --git a/src/soc/qualcomm/common/spi.c b/src/soc/qualcomm/common/spi.c index b4db3e589c..aee124dd59 100644 --- a/src/soc/qualcomm/common/spi.c +++ b/src/soc/qualcomm/common/spi.c @@ -3,6 +3,7 @@ #include #include #include +#include static const struct spi_ctrlr qspi_ctrlr = { .claim_bus = qspi_claim_bus, @@ -12,12 +13,24 @@ static const struct spi_ctrlr qspi_ctrlr = { .max_xfer_size = QSPI_MAX_PACKET_COUNT, }; +const struct spi_ctrlr spi_qup_ctrlr = { + .claim_bus = qup_spi_claim_bus, + .release_bus = qup_spi_release_bus, + .xfer = qup_spi_xfer, + .max_xfer_size = 65535, +}; + const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, + { + .ctrlr = &spi_qup_ctrlr, + .bus_start = 0, + .bus_end = 15, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- cgit v1.2.3