From 6c14cd32ae71c89b286c6ea0aa07671eb94d03ee Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 11 Jan 2018 16:25:28 -0800 Subject: mainboard/google/kahlee: Finish GPIO90 setup for Grunt GPIO 90 is being used as a GPIO. The IOMUX register is set correctly, but these additional registers need to be set to use it as a GPIO. - Split structures into variant specific versions. These will be moved into the variant tree in a follow-on patch - Set GENINT_DISABLE bit - Disable interrupts for this GPIO. BUG=b:71867096 TEST=Build and boot grunt. Verify registers are set correctly. Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/23228 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/mainboard.c | 46 +++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 0954a2923b..b080682b69 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -39,6 +39,9 @@ * These values are used by the PCI configuration space, * MP Tables. TODO: Make ACPI use these values too. */ + +// TODO: Move these to board variant specific file +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE) const u8 mainboard_picr_data[] = { [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, @@ -76,7 +79,45 @@ const u8 mainboard_intr_data[] = { [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; +#else +const u8 mainboard_picr_data[] = { + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, + [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +}; +const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +#endif /* PIRQ Setup */ static void pirq_setup(void) { @@ -96,6 +137,11 @@ static void mainboard_init(void *chip_info) gpes = get_gpe_table(&num); gpe_configure_sci(gpes, num); + + /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */ + if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)) + pm_write8(PM_PCIB_CFG, + pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); } /************************************************* -- cgit v1.2.3